[coreboot-gerrit] Patch set updated for coreboot: 53840ee broadwell: Preparations for building
Marc Jones (marc.jones@se-eng.com)
gerrit at coreboot.org
Tue Dec 30 19:34:03 CET 2014
Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7939
-gerrit
commit 53840ee3a170e020bd00341c1f7e96dc3cfa8441
Author: Marc Jones <marc.jones at se-eng.com>
Date: Fri Dec 26 22:11:14 2014 -0700
broadwell: Preparations for building
Updated the Broadwell for differences in the source based on
the chromium tree. It is missing most of the recent updates
on coreboot.org.
- makefile changes for Elog and IDF tool
- kconfig changes for ME, ucode, and other updates
- update oprom flag
- update timestamp mechanism
- cbfs payload function is now generic
Change-Id: I82bd0792e9dcf81085246873164de6600528d6fe
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
---
src/soc/intel/broadwell/Kconfig | 61 +++++++++++++++++++++--
src/soc/intel/broadwell/Makefile.inc | 33 +++++++++---
src/soc/intel/broadwell/bootblock/cpu.c | 2 +-
src/soc/intel/broadwell/chip.c | 2 +-
src/soc/intel/broadwell/cpu.c | 4 --
src/soc/intel/broadwell/ehci.c | 1 -
src/soc/intel/broadwell/igd.c | 23 ++-------
src/soc/intel/broadwell/romstage/cache_as_ram.inc | 1 -
src/soc/intel/broadwell/romstage/raminit.c | 2 +-
src/soc/intel/broadwell/romstage/romstage.c | 26 +++++++---
src/soc/intel/broadwell/spi.c | 10 ++--
src/soc/intel/broadwell/spi_loading.c | 26 ----------
src/soc/intel/broadwell/systemagent.c | 14 +++---
13 files changed, 122 insertions(+), 83 deletions(-)
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 1498489..24922a1 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -30,6 +30,7 @@ config CPU_SPECIFIC_OPTIONS
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select RELOCATABLE_MODULES
+ select RELOCATABLE_RAMSTAGE
select REG_SCRIPT
select PARALLEL_MP
select PCIEXP_ASPM
@@ -39,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS
select SMP
select SPI_FLASH
select SSE2
+ select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_CONSTANT_RATE
select TSC_SYNC_MFENCE
select UDELAY_TSC
@@ -56,9 +58,6 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "soc/intel/broadwell/bootblock/pch.c"
-config MICROCODE_INCLUDE_PATH
- string
- default "src/soc/intel/broadwell/microcode"
config MMCONF_BASE_ADDRESS
hex
@@ -208,6 +207,62 @@ config SERIRQ_CONTINUOUS_MODE
help
If you set this option to y, the serial IRQ machine will be
operated in continuous mode.
+config HAVE_ME_BIN
+ bool "Add Intel Management Engine firmware"
+ default y
+ help
+ The Intel processor in the selected system requires a special firmware
+ for an integrated controller called Management Engine (ME). The ME
+ firmware might be provided in coreboot's 3rdparty repository. If
+ not and if you don't have the firmware elsewhere, you can still
+ build coreboot without it. In this case however, you'll have to make
+ sure that you don't overwrite your ME firmware on your flash ROM.
+
+config ME_BIN_PATH
+ string "Path to management engine firmware"
+ depends on HAVE_ME_BIN
+ default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin"
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config BUILD_WITH_FAKE_IFD
+ bool "Build with a fake IFD"
+ default y if !HAVE_IFD_BIN
+ help
+ If you don't have an Intel Firmware Descriptor (ifd.bin) for your
+ board, you can select this option and coreboot will build without it.
+ Though, the resulting coreboot.rom will not contain all parts required
+ to get coreboot running on your board. You can however write only the
+ BIOS section to your board's flash ROM and keep the other sections
+ untouched. Unfortunately the current version of flashrom doesn't
+ support this yet. But there is a patch pending [1].
+
+ WARNING: Never write a complete coreboot.rom to your flash ROM if it
+ was built with a fake IFD. It just won't work.
+
+ [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
+
+config IFD_BIOS_SECTION
+ depends on BUILD_WITH_FAKE_IFD
+ string
+ default ""
+
+config IFD_ME_SECTION
+ depends on BUILD_WITH_FAKE_IFD
+ string
+ default ""
+
+config IFD_PLATFORM_SECTION
+ depends on BUILD_WITH_FAKE_IFD
+ string
+ default ""
+
+config IFD_BIN_PATH
+ string "Path to intel firmware descriptor"
+ depends on !BUILD_WITH_FAKE_IFD
+ default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"
config ME_MBP_CLEAR_LATE
bool "Defer wait for ME MBP Cleared"
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 1de2a01..43be95e 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -13,7 +13,7 @@ ramstage-y += acpi.c
ramstage-y += adsp.c
ramstage-y += chip.c
ramstage-y += cpu.c
-ramstage-y += elog.c
+ramstage-$(CONFIG_ELOG) += elog.c
ramstage-y += finalize.c
ramstage-y += gpio.c
romstage-y += gpio.c
@@ -69,20 +69,38 @@ romstage-y += usbdebug.c
smm-y += usbdebug.c
endif
-INCLUDES += -Isrc/soc/intel/broadwell/
+CPPFLAGS_common += -Isrc/soc/intel/broadwell/
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
# image outside of CBFS
-INTERMEDIATE := pch_add_me
+INTERMEDIATE := broadwell_add_me
-pch_add_me: $(obj)/coreboot.pre $(IFDTOOL)
+ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
+IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
+IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
+ $(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
+ $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
+else
+IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
+endif
+
+broadwell_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
+ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
+ printf "\n** WARNING **\n"
+ printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
+ printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
+ printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
+ printf " IFDFAKE Building a fake Intel Firmware Descriptor\n"
+ $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
+endif
printf " DD Adding Intel Firmware Descriptor\n"
- dd if=3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin \
+ dd if=$(IFD_BIN_PATH) \
of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
+ifeq ($(CONFIG_HAVE_ME_BIN),y)
printf " IFDTOOL me.bin -> coreboot.pre\n"
$(objutil)/ifdtool/ifdtool \
- -i ME:3rdparty/mainboard/$(MAINBOARDDIR)/me.bin \
+ -i ME:$(CONFIG_ME_BIN_PATH) \
$(obj)/coreboot.pre
mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
@@ -94,8 +112,9 @@ else
$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
endif
+endif
-PHONY += pch_add_me
+PHONY += broadwell_add_me
# If an MRC file is an ELF file determine the entry address and first loadable
# section offset in the file. Subtract the offset from the entry address to
diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c
index da7b99d..e20ced2 100644
--- a/src/soc/intel/broadwell/bootblock/cpu.c
+++ b/src/soc/intel/broadwell/bootblock/cpu.c
@@ -48,7 +48,7 @@ static void enable_rom_caching(void)
disable_cache();
/* Why only top 4MiB ? */
- set_var_mtrr(1, CACHE_ROM_BASE, CONFIG_CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
+ set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
enable_cache();
/* Enable Variable MTRRs */
diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c
index 2a12820..eecb0cf 100644
--- a/src/soc/intel/broadwell/chip.c
+++ b/src/soc/intel/broadwell/chip.c
@@ -33,7 +33,7 @@ static struct device_operations pci_domain_ops = {
.read_resources = &pci_domain_read_resources,
.set_resources = &pci_domain_set_resources,
.scan_bus = &pci_domain_scan_bus,
- .ops_pci_bus = &pci_ops_mmconf,
+ .ops_pci_bus = &pci_bus_default_ops,
};
static struct device_operations cpu_bus_ops = {
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index afd2dcb..b46c2e2 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -36,7 +36,6 @@
#include <cpu/x86/smm.h>
#include <delay.h>
#include <pc80/mc146818rtc.h>
-#include <usbdebug.h>
#include <broadwell/cpu.h>
#include <broadwell/msr.h>
#include <broadwell/pci_devs.h>
@@ -718,7 +717,4 @@ void broadwell_init_cpus(device_t dev)
/* Restore the default SMM region. */
restore_default_smm_area(smm_save_area);
-
- /* Enable ROM caching if option was selected. */
- x86_mtrr_enable_rom_caching();
}
diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c
index a59d3c8..2b8a9be 100644
--- a/src/soc/intel/broadwell/ehci.c
+++ b/src/soc/intel/broadwell/ehci.c
@@ -23,7 +23,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <usbdebug.h>
#include <arch/io.h>
#include <broadwell/ehci.h>
#include <broadwell/pch.h>
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index b429758..0f27fec 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -18,6 +18,7 @@
*/
#include <arch/io.h>
+#include <bootmode.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
@@ -472,7 +473,6 @@ static void igd_init(struct device *dev)
{
int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
u32 rp1_gfx_freq;
- extern int oprom_is_loaded;
/* IGD needs to be Bus Master */
u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
@@ -512,7 +512,7 @@ static void igd_init(struct device *dev)
reg_script_run_on_dev(dev, haswell_late_init_script);
}
- if (!oprom_is_loaded) {
+ if (!gfx_get_init_done()) {
/*
* Enable DDI-A if the Option ROM did not execute:
*
@@ -525,25 +525,8 @@ static void igd_init(struct device *dev)
}
}
-static void igd_read_resources(struct device *dev)
-{
- pci_dev_read_resources(dev);
-
-#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB
- struct resource *res;
-
- /* Set the graphics memory to write combining. */
- res = find_resource(dev, PCI_BASE_ADDRESS_2);
- if (res == NULL) {
- printk(BIOS_DEBUG, "gma: memory resource not found.\n");
- return;
- }
- res->flags |= IORESOURCE_WRCOMB;
-#endif
-}
-
static struct device_operations igd_ops = {
- .read_resources = &igd_read_resources,
+ .read_resources = &pci_dev_read_resources,
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.init = &igd_init,
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index 029ab7c..4e6cf09 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -19,7 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index d4ebc08..7217bb9 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -85,7 +85,7 @@ void raminit(struct pei_data *pei_data)
/* Determine if mrc.bin is in the cbfs. */
entry = (pei_wrapper_entry_t)cbfs_get_file_content(
- CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab);
+ CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab, NULL);
if (entry == NULL) {
printk(BIOS_DEBUG, "Couldn't find mrc.bin\n");
return;
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 1d5ee89..4a5a47c 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -31,7 +31,6 @@
#include <ramstage_cache.h>
#include <romstage_handoff.h>
#include <timestamp.h>
-#include <vendorcode/google/chromeos/chromeos.h>
#include <broadwell/me.h>
#include <broadwell/pei_data.h>
#include <broadwell/pm.h>
@@ -39,6 +38,20 @@
#include <broadwell/romstage.h>
#include <broadwell/spi.h>
+static inline uint64_t timestamp_get(void)
+{
+ return rdtscll();
+}
+
+static inline tsc_t ts64_to_tsc(uint64_t ts)
+{
+ tsc_t tsc = {
+ .lo = ts,
+ .hi = ts >> 32,
+ };
+ return tsc;
+}
+
static inline void mark_ts(struct romstage_params *rp, uint64_t ts)
{
struct romstage_timestamps *rt = &rp->ts;
@@ -129,19 +142,16 @@ void romstage_common(struct romstage_params *params)
chromeos_init(params->power_state->prev_sleep_state);
/* Save timestamp information. */
- timestamp_init(params->ts.times[0]);
- timestamp_add(TS_START_ROMSTAGE, params->ts.times[1]);
- timestamp_add(TS_BEFORE_INITRAM, params->ts.times[2]);
- timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]);
+ timestamp_init(ts64_to_tsc(params->ts.times[0]));
+ timestamp_add(TS_START_ROMSTAGE, ts64_to_tsc(params->ts.times[1]));
+ timestamp_add(TS_BEFORE_INITRAM, ts64_to_tsc(params->ts.times[2]));
+ timestamp_add(TS_AFTER_INITRAM, ts64_to_tsc(params->ts.times[3]));
}
void asmlinkage romstage_after_car(void)
{
timestamp_add_now(TS_END_ROMSTAGE);
- /* Run vboot verification if configured. */
- vboot_verify_firmware(romstage_handoff_find_or_add());
-
/* Load the ramstage. */
copy_and_run();
while (1);
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index 935c532..eeffda0 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -30,8 +30,6 @@
#include <spi-generic.h>
#include <broadwell/pci_devs.h>
-#define min(a, b) ((a)<(b)?(a):(b))
-
#ifdef __SMM__
#define pci_read_config_byte(dev, reg, targ)\
*(targ) = pci_read_config8(dev, reg)
@@ -488,6 +486,11 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
return -1;
}
+unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
+{
+ return min(cntlr.databytes, buf_len);
+}
+
int spi_xfer(struct spi_slave *slave, const void *dout,
unsigned int bytesout, void *din, unsigned int bytesin)
{
@@ -588,7 +591,8 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
while (trans.bytesout || trans.bytesin) {
uint32_t data_length;
- /* SPI addresses are 24 bit only */http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/pentium-n3520-j2850-celeron-n2920-n2820-n2815-n2806-j1850-j1750-datasheet.pdf
+ /* SPI addresses are 24 bit only */
+ /* http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/pentium-n3520-j2850-celeron-n2920-n2820-n2815-n2806-j1850-j1750-datasheet.pdf */
writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
if (trans.bytesout)
diff --git a/src/soc/intel/broadwell/spi_loading.c b/src/soc/intel/broadwell/spi_loading.c
index d7247c6..9454d03 100644
--- a/src/soc/intel/broadwell/spi_loading.c
+++ b/src/soc/intel/broadwell/spi_loading.c
@@ -65,29 +65,3 @@ static inline void *spi_mirror(void *file_start, int file_len)
/* Provide pointer into mirrored space. */
return &dest[alignment_diff];
}
-
-void *cbfs_load_payload(struct cbfs_media *media, const char *name)
-{
- int file_len;
- void *file_start;
- struct cbfs_file *file;
-
- file_start = vboot_get_payload(&file_len);
-
- if (file_start != NULL)
- return spi_mirror(file_start, file_len);
-
- file = cbfs_get_file(media, name);
-
- if (file == NULL)
- return NULL;
-
- if (ntohl(file->type) != CBFS_TYPE_PAYLOAD)
- return NULL;
-
- file_len = ntohl(file->len);
-
- file_start = CBFS_SUBHEADER(file);
-
- return spi_mirror(file_start, file_len);
-}
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index 7fc45a3..74c43f2 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -446,13 +446,13 @@ unsigned long acpi_fill_srat(unsigned long current)
}
static struct device_operations systemagent_ops = {
- .read_resources = systemagent_read_resources,
- .acpi_fill_ssdt_generator = generate_cpu_entries,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = systemagent_init,
- .enable = systemagent_enable,
- .ops_pci = broadwell_pci_ops,
+ .read_resources = &systemagent_read_resources,
+ .acpi_fill_ssdt_generator = &generate_cpu_entries,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+ .init = &systemagent_init,
+ .enable = &systemagent_enable,
+ .ops_pci = &broadwell_pci_ops,
};
static const unsigned short systemagent_ids[] = {
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