[coreboot-gerrit] Patch set updated for coreboot: a432aff storm: initialize dynamic cbmem properly

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7999

-gerrit

commit a432aff018d7f8bcd03bdc6ec6758878032f315f
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Tue May 13 17:17:22 2014 -0700

    storm: initialize dynamic cbmem properly
    
    Dynamic cbmem support has been enabled on storm, but the proper
    initialization at romstage is missing.
    
    Proper DRAM base address definition is also necessary so that CBMEM is
    placed in the correct address range (presently at the top of DRAM).
    
    BUG=chrome-os-partner:27784
    
    TEST=build boot coreboot on ap148, observe the following in the
         console output:
    
      Wrote coreboot table at: 5fffd000, 0xe8 bytes, checksum 44a5
      coreboot table: 256 bytes.
      CBMEM ROOT  0. 5ffff000 00001000
      COREBOOT    1. 5fffd000 00002000
    
    Original-Change-Id: I74ccd252ddfdeaa0a5bcc929be72be174f310730
    Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/199674
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    (cherry picked from commit e2aeb2f4e7f3959d5f5336f42a29909134a7ddb7)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: I9358a65756ef97dc88493c55d69a5673832a22b0
---
 src/mainboard/google/storm/romstage.c |  2 ++
 src/soc/qualcomm/ipq806x/Kconfig      | 11 +++++++----
 src/soc/qualcomm/ipq806x/Makefile.inc |  1 +
 3 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/storm/romstage.c b/src/mainboard/google/storm/romstage.c
index 6fadedf..85d6b48 100644
--- a/src/mainboard/google/storm/romstage.c
+++ b/src/mainboard/google/storm/romstage.c
@@ -19,12 +19,14 @@
 
 #include <arch/stages.h>
 #include <cbfs.h>
+#include <cbmem.h>
 #include <console/console.h>
 
 void main(void)
 {
 	void *entry;
 
+	cbmem_initialize_empty();
 	console_init();
 
 	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig
index 385c793..cf11177 100644
--- a/src/soc/qualcomm/ipq806x/Kconfig
+++ b/src/soc/qualcomm/ipq806x/Kconfig
@@ -51,6 +51,9 @@ config RAMSTAGE_BASE
 	hex
 	default 0x4060c000
 
+config SYS_SDRAM_BASE
+	hex
+	default 0x40000000
 
 config STACK_TOP
 	hex
@@ -61,11 +64,11 @@ config STACK_BOTTOM
 	default 0x405fc000
 
 config CBFS_CACHE_ADDRESS
-        hex "memory address to put CBFS cache data"
-        default 0x405e6000
+	hex "memory address to put CBFS cache data"
+	default 0x405e6000
 
 config CBFS_CACHE_SIZE
-        hex "size of CBFS cache data"
-        default 0x00016000
+	hex "size of CBFS cache data"
+	default 0x00016000
 
 endif
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc
index 2379d63..68829e2 100644
--- a/src/soc/qualcomm/ipq806x/Makefile.inc
+++ b/src/soc/qualcomm/ipq806x/Makefile.inc
@@ -29,6 +29,7 @@ romstage-y += gpio.c
 romstage-$(CONFIG_SPI_FLASH) += spi.c
 romstage-y += timer.c
 romstage-$(CONFIG_DRIVERS_UART) += uart.c
+romstage-$(CONFIG_DYNAMIC_CBMEM) += cbmem.c
 
 ramstage-y += cbmem.c
 ramstage-y += clock.c