[coreboot-gerrit] Patch set updated for coreboot: feb7bd3 intel/bd82x6x: Allow limiting of SATA speed in CMOS config
Alexandru Gagniuc (mr.nuke.me@gmail.com)
gerrit at coreboot.org
Thu Feb 6 02:26:26 CET 2014
Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4823
-gerrit
commit feb7bd3fffa3e1ec3ab29640478696c0f71984dc
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date: Sun Jan 26 11:36:07 2014 -0600
intel/bd82x6x: Allow limiting of SATA speed in CMOS config
Up until now, the only way to limit SATA speed was via devicetree.cb,
which required recompiling coreboot in order to lift this limit.
However, there are cases where limiting is still desirable with the
option to lift the limit later. To accommodate this, still check
devicetree first, but if no hard limit is specified, then use CMOS
to check if the user desires to limit the speed.
google buterfly and stout are limited by default to Gen2 speeds due
to issues with buggy SSD firmware.
Change-Id: I0d6ac67416edcb28eb2a9091c86dc0a22d7b1d3f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
src/mainboard/google/butterfly/cmos.default | 1 +
src/mainboard/google/butterfly/cmos.layout | 7 ++++++-
src/mainboard/google/link/cmos.layout | 7 ++++++-
src/mainboard/google/parrot/cmos.layout | 7 ++++++-
src/mainboard/google/stout/cmos.default | 1 +
src/mainboard/google/stout/cmos.layout | 7 ++++++-
src/mainboard/intel/emeraldlake2/cmos.layout | 7 ++++++-
src/mainboard/kontron/ktqm77/cmos.layout | 7 ++++++-
src/mainboard/lenovo/x230/cmos.default | 3 ++-
src/mainboard/lenovo/x230/cmos.layout | 7 ++++++-
src/mainboard/samsung/lumpy/cmos.layout | 7 ++++++-
src/mainboard/samsung/stumpy/cmos.layout | 7 ++++++-
src/southbridge/intel/bd82x6x/sata.c | 22 ++++++++++++++++++----
13 files changed, 76 insertions(+), 14 deletions(-)
diff --git a/src/mainboard/google/butterfly/cmos.default b/src/mainboard/google/butterfly/cmos.default
index 77c7100..bc08ed9 100644
--- a/src/mainboard/google/butterfly/cmos.default
+++ b/src/mainboard/google/butterfly/cmos.default
@@ -4,3 +4,4 @@ debug_level = Spew
nmi = Enable
power_on_after_fail = Enable
sata_mode = AHCI
+sata_speed_limit = Gen2
diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout
index f0163f1..222d41b 100644
--- a/src/mainboard/google/butterfly/cmos.layout
+++ b/src/mainboard/google/butterfly/cmos.layout
@@ -88,7 +88,8 @@ entries
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
411 1 e 8 sata_mode
-#412 4 r 0 unused
+412 2 e 9 sata_speed_limit
+#414 2 r 0 unused
# coreboot config options: bootloader
#Used by ChromeOS:
@@ -137,6 +138,10 @@ enumerations
7 2 Keep
8 0 AHCI
8 1 Compatible
+9 0 None
+9 1 Gen1
+9 2 Gen2
+9 3 Gen3
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout
index b7320b5..b9a1178 100644
--- a/src/mainboard/google/link/cmos.layout
+++ b/src/mainboard/google/link/cmos.layout
@@ -86,7 +86,8 @@ entries
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
411 1 e 8 sata_mode
-#412 4 r 0 unused
+412 2 e 9 sata_speed_limit
+#414 2 r 0 unused
# coreboot config options: bootloader
#Used by ChromeOS:
@@ -134,6 +135,10 @@ enumerations
7 2 Keep
8 0 AHCI
8 1 Compatible
+9 0 None
+9 1 Gen1
+9 2 Gen2
+9 3 Gen3
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout
index b7320b5..b9a1178 100644
--- a/src/mainboard/google/parrot/cmos.layout
+++ b/src/mainboard/google/parrot/cmos.layout
@@ -86,7 +86,8 @@ entries
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
411 1 e 8 sata_mode
-#412 4 r 0 unused
+412 2 e 9 sata_speed_limit
+#414 2 r 0 unused
# coreboot config options: bootloader
#Used by ChromeOS:
@@ -134,6 +135,10 @@ enumerations
7 2 Keep
8 0 AHCI
8 1 Compatible
+9 0 None
+9 1 Gen1
+9 2 Gen2
+9 3 Gen3
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/google/stout/cmos.default b/src/mainboard/google/stout/cmos.default
index 77c7100..bc08ed9 100644
--- a/src/mainboard/google/stout/cmos.default
+++ b/src/mainboard/google/stout/cmos.default
@@ -4,3 +4,4 @@ debug_level = Spew
nmi = Enable
power_on_after_fail = Enable
sata_mode = AHCI
+sata_speed_limit = Gen2
diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout
index f0163f1..222d41b 100644
--- a/src/mainboard/google/stout/cmos.layout
+++ b/src/mainboard/google/stout/cmos.layout
@@ -88,7 +88,8 @@ entries
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
411 1 e 8 sata_mode
-#412 4 r 0 unused
+412 2 e 9 sata_speed_limit
+#414 2 r 0 unused
# coreboot config options: bootloader
#Used by ChromeOS:
@@ -137,6 +138,10 @@ enumerations
7 2 Keep
8 0 AHCI
8 1 Compatible
+9 0 None
+9 1 Gen1
+9 2 Gen2
+9 3 Gen3
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout
index b7320b5..b9a1178 100644
--- a/src/mainboard/intel/emeraldlake2/cmos.layout
+++ b/src/mainboard/intel/emeraldlake2/cmos.layout
@@ -86,7 +86,8 @@ entries
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
411 1 e 8 sata_mode
-#412 4 r 0 unused
+412 2 e 9 sata_speed_limit
+#414 2 r 0 unused
# coreboot config options: bootloader
#Used by ChromeOS:
@@ -134,6 +135,10 @@ enumerations
7 2 Keep
8 0 AHCI
8 1 Compatible
+9 0 None
+9 1 Gen1
+9 2 Gen2
+9 3 Gen3
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout
index dc6a44b..410b464 100644
--- a/src/mainboard/kontron/ktqm77/cmos.layout
+++ b/src/mainboard/kontron/ktqm77/cmos.layout
@@ -86,7 +86,8 @@ entries
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
411 1 e 11 sata_mode
-#412 4 r 0 unused
+412 2 e 12 sata_speed_limit
+#414 2 r 0 unused
# coreboot config options: additional mainboard options
416 4 e 10 systemp_type
@@ -165,6 +166,10 @@ enumerations
10 4 LM75 at 9e
11 0 AHCI
11 1 Compatible
+12 0 None
+12 1 Gen1
+12 2 Gen2
+12 3 Gen3
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
index 137f482..f8c5105 100644
--- a/src/mainboard/lenovo/x230/cmos.default
+++ b/src/mainboard/lenovo/x230/cmos.default
@@ -11,8 +11,9 @@ wwan=Enable
wlan=Enable
touchpad=Enable
sata_mode=AHCI
+sata_speed_limit=None
fn_ctrl_swap=Disable
sticky_fn=Disable
trackpoint=Enable
hyper_threading=Enable
-backlight=Both
\ No newline at end of file
+backlight=Both
diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout
index 6f8822f..ad4bfb9 100644
--- a/src/mainboard/lenovo/x230/cmos.layout
+++ b/src/mainboard/lenovo/x230/cmos.layout
@@ -94,10 +94,11 @@ entries
416 1 e 1 trackpoint
417 1 e 1 fn_ctrl_swap
418 1 e 1 sticky_fn
-#419 2 r 0 unused
+419 2 e 11 sata_speed_limit
421 1 e 9 sata_mode
422 2 e 10 backlight
+
# coreboot config options: cpu
424 1 e 2 hyper_threading
@@ -150,6 +151,10 @@ enumerations
10 1 Keyboard only
10 2 Thinklight only
10 3 None
+11 0 None
+11 1 Gen1
+11 2 Gen2
+11 3 Gen3
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/samsung/lumpy/cmos.layout b/src/mainboard/samsung/lumpy/cmos.layout
index 208e8ee..feff985 100644
--- a/src/mainboard/samsung/lumpy/cmos.layout
+++ b/src/mainboard/samsung/lumpy/cmos.layout
@@ -86,7 +86,8 @@ entries
408 1 e 1 nmi
#409 2 e 7 power_on_after_fail
411 1 e 8 sata_mode
-#412 4 r 0 unused
+412 2 e 9 sata_speed_limit
+#414 2 r 0 unused
# coreboot config options: bootloader
#Used by ChromeOS:
@@ -134,6 +135,10 @@ enumerations
7 2 Keep
8 0 AHCI
8 1 Compatible
+9 0 None
+9 1 Gen1
+9 2 Gen2
+9 3 Gen3
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/samsung/stumpy/cmos.layout b/src/mainboard/samsung/stumpy/cmos.layout
index ec393a5..27a35f4 100644
--- a/src/mainboard/samsung/stumpy/cmos.layout
+++ b/src/mainboard/samsung/stumpy/cmos.layout
@@ -85,7 +85,8 @@ entries
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
411 1 e 8 sata_mode
-#412 4 r 0 unused
+412 2 e 9 sata_speed_limit
+#414 2 r 0 unused
# coreboot config options: bootloader
#Used by ChromeOS:
@@ -134,6 +135,10 @@ enumerations
7 2 Keep
8 0 AHCI
8 1 Compatible
+9 0 None
+9 1 Gen1
+9 2 Gen2
+9 3 Gen3
# -----------------------------------------------------------------
checksums
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 8d12202..29be69e 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -46,7 +46,7 @@ static void sata_init(struct device *dev)
u16 reg16;
/* Get the chip configuration */
config_t *config = dev->chip_info;
- u8 sata_mode;
+ u8 sata_mode, sata_limit;
printk(BIOS_DEBUG, "SATA: Initializing...\n");
@@ -106,12 +106,26 @@ static void sata_init(struct device *dev)
reg32 = read32(abar + 0x00);
reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
reg32 &= ~0x00020060; // clear SXS+EMS+PMS
- /* Set ISS, if available */
+ /* Set ISS, if available
+ * Try devicetree.cb first, for hard limit, otherwise look in
+ * CMOS for user-selectable limit
+ */
if (config->sata_interface_speed_limit)
{
+ printk(BIOS_INFO, "Applying hard limit on SATA speed");
+ sata_limit = config->sata_interface_speed_limit;
+ } else {
+ /* Default to no limit if not configured in CMOS */
+ if (get_option(&sata_limit, "sata_speed_limit")
+ != CB_SUCCESS)
+ sata_limit = 0;
+ }
+ sata_limit &= 0x03;
+ if (sata_limit) {
+ printk(BIOS_INFO, "Limiting SATA speed to Gen%d\n",
+ sata_limit);
reg32 &= ~0x00f00000;
- reg32 |= (config->sata_interface_speed_limit & 0x03)
- << 20;
+ reg32 |= sata_limit << 20;
}
write32(abar + 0x00, reg32);
/* PI (Ports implemented) */
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