[coreboot-gerrit] Patch merged into coreboot/master: 0ed3ab7 baytrail: adjust cache policy during romstage

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 0ed3ab7d8619eb3fb0fe61d3990f2d2a91f3b00b
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Oct 7 16:24:44 2013 -0500

    baytrail: adjust cache policy during romstage
    
    The caching policy for romstage was previously using a 32KiB
    of cache-as-ram for both the MRC wrapper and the romstage stack/data.
    It also used a 32KiB code cache region. The BWG's limitations for
    the code and data region before memory is up was wrong. It consists
    of a 16-way set associative 1MiB cache. As long as enough addresses
    are not read there isn't a risk of evicting the data/stack.
    
    Now create a 64KiB cache-as-ram region split evenly between romstage
    and the MRC wrapper. Additionally cache the memory just below
    4GiB in CBFS size. This will cover any code and read-only data needed.
    
    BUG=chrome-os-partner:22858
    BRANCH=None
    TEST=Built and booted quickly with corresponding changes to MRC warpper.
    CQ-DEPEND=CL:*146175
    
    Change-Id: I021cecb886a9c0622005edc389136d22905d4520
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/172150
    Reviewed-by: Duncan Laurie <dlaurie at chromium.org>


See http://review.coreboot.org/4868 for details.

-gerrit