[coreboot-gerrit] Patch set updated for coreboot: e2ea60e NOTFORMERGE: lenovo/x60: Enable Infrared port.
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Wed Feb 12 17:08:41 CET 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5170
-gerrit
commit e2ea60e4589be1cddf90e4b55a1b01cfa653e0b0
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Sun Feb 9 02:17:26 2014 +0100
NOTFORMERGE: lenovo/x60: Enable Infrared port.
Change-Id: I251031086dd5ac012e3dc2e8fed816a8ca629f15
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/mainboard/lenovo/x60/acpi/superio.asl | 18 ++++++++++++++++++
src/mainboard/lenovo/x60/devicetree.cb | 4 ++++
src/mainboard/lenovo/x60/romstage.c | 2 +-
3 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x60/acpi/superio.asl b/src/mainboard/lenovo/x60/acpi/superio.asl
index 6786da7..c07b336 100644
--- a/src/mainboard/lenovo/x60/acpi/superio.asl
+++ b/src/mainboard/lenovo/x60/acpi/superio.asl
@@ -16,6 +16,24 @@
}
#endif
+ Device (FIR) // Infrared
+ {
+ Name(_HID, EISAID("IBM0071"))
+ Name(_CID, EISAID("PNP0511"))
+ Name(_UID, 1)
+
+ Name(_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x2f8, 0x2f8, 0x01, 0x08)
+ IRQNoFlags () {3}
+ })
+
+ Method (_STA, 0)
+ {
+ Return (0xf)
+ }
+ }
+
Device (COMA) // Serial
{
Name(_HID, EISAID("PNP0501"))
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index 5b4e37f..acd5af3 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -125,6 +125,10 @@ chip northbridge/intel/i945
chip superio/nsc/pc87382
device pnp 164e.2 on # IR
io 0x60 = 0x2f8
+ irq 0x29 = 0xb0
+ irq 0x70 = 0x3
+ drq 0x74 = 0x1
+ irq 0xf0 = 0x82
end
device pnp 164e.3 on # Digitizer
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 1198fb2..8eca464 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -86,7 +86,7 @@ static void ich7_enable_lpc(void)
// decode range
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0f);
/* range 0x1600 - 0x167f */
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601);
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