[coreboot-gerrit] Patch set updated for coreboot: ea3c978 lenovo/t60: Enable Infrared port.
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Sat Feb 15 21:09:12 CET 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5243
-gerrit
commit ea3c97897d321a597af8536d8a4a64e913edb644
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Sat Feb 15 19:17:10 2014 +0100
lenovo/t60: Enable Infrared port.
Change-Id: I10f05334328c9929a99352185d286a7a17898801
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/mainboard/lenovo/t60/acpi/superio.asl | 16 ++++++++++++++++
src/mainboard/lenovo/t60/devicetree.cb | 4 ++++
src/mainboard/lenovo/t60/romstage.c | 2 +-
3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/t60/acpi/superio.asl b/src/mainboard/lenovo/t60/acpi/superio.asl
index e69de29..a0d8e0a 100644
--- a/src/mainboard/lenovo/t60/acpi/superio.asl
+++ b/src/mainboard/lenovo/t60/acpi/superio.asl
@@ -0,0 +1,16 @@
+ Device (FIR) // Infrared
+ {
+ Name(_HID, EISAID("IBM0071"))
+ Name(_CID, EISAID("PNP0511"))
+
+ Name(_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x2f8, 0x2f8, 0x01, 0x08)
+ IRQNoFlags () {3}
+ })
+
+ Method (_STA, 0)
+ {
+ Return (0xf)
+ }
+ }
diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
index b87a223..cce5f93 100644
--- a/src/mainboard/lenovo/t60/devicetree.cb
+++ b/src/mainboard/lenovo/t60/devicetree.cb
@@ -148,6 +148,10 @@ chip northbridge/intel/i945
chip superio/nsc/pc87382
device pnp 164e.2 on # IR
io 0x60 = 0x2f8
+ irq 0x29 = 0xb0
+ irq 0x70 = 0x3
+ drq 0x74 = 0x1
+ irq 0xf0 = 0x82
end
device pnp 164e.3 off # Serial Port
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index dae917c..237e967 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -79,7 +79,7 @@ static void ich7_enable_lpc(void)
// decode range
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0f);
/* range 0x1600 - 0x167f */
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601);
More information about the coreboot-gerrit
mailing list