[coreboot-gerrit] Patch set updated for coreboot: 893880d baytrail: correct MMC pci location
Aaron Durbin (adurbin@google.com)
gerrit at coreboot.org
Tue Jan 28 05:29:10 CET 2014
Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4884
-gerrit
commit 893880d0c47578cec3196edb5a92286de84317f9
Author: Aaron Durbin <adurbin at chromium.org>
Date: Fri Oct 11 08:39:54 2013 -0500
baytrail: correct MMC pci location
The original documentation was incorrect. Fix the pci
device for the MMC port to reflect reality.
MMC is at 00:17.0 with a device id of 0x0f50.
BUG=None
BRANCH=None
TEST=Built.
Change-Id: Ic18665b7dda5f386e72d1a5255e4e57d5b631eb0
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172772
Reviewed-by: Shawn Nematbakhsh <shawnn at chromium.org>
---
src/soc/intel/baytrail/baytrail/pci_devs.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/soc/intel/baytrail/baytrail/pci_devs.h b/src/soc/intel/baytrail/baytrail/pci_devs.h
index 46c6ea6..8b0335e 100644
--- a/src/soc/intel/baytrail/baytrail/pci_devs.h
+++ b/src/soc/intel/baytrail/baytrail/pci_devs.h
@@ -32,11 +32,6 @@
#define GFX_FUNC 0
# define GFX_DEVID 0x0f31
-/* MMC Port */
-#define MMC_DEV 16
-#define MMC_FUNC 0
-# define MMC_DEVID 0x0f14
-
/* SDIO Port */
#define SDIO_DEV 17
#define SDIO_FUNC 0
@@ -63,6 +58,11 @@
#define LPE_FUNC 0
# define LPE_DEVID 0x0f28
+/* MMC Port */
+#define MMC_DEV 23
+#define MMC_FUNC 0
+# define MMC_DEVID 0x0f50
+
/* Serial IO 1 */
#define SIO1_DEV 24
# define SIO_DMA1_DEV SIO1_DEV
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