[coreboot-gerrit] Patch set updated for coreboot: 06f7535 rambi: Enable internal keyboard

Aaron Durbin (adurbin@google.com) gerrit at coreboot.org
Tue Jan 28 05:41:16 CET 2014


Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4915

-gerrit

commit 06f7535264b57560e4d8f0f3c89597960c6b7b01
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Oct 31 10:10:20 2013 -0700

    rambi: Enable internal keyboard
    
    The EC LPC init function needs to run to enable the internal keyboard.
    
    I needed this to confirm that it is just USB keyboards that are causing
    all sorts of issues.
    
    BUG=chrome-os-partner:23635
    BRANCH=rambi
    TEST=boot to recovery screen and hit tab
    
    Change-Id: Iea0fc66ba62ea7da71ef83c26e25ae32bef102bd
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175207
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/rambi/devicetree.cb | 10 +++++++++-
 src/soc/intel/baytrail/southcluster.c    |  2 +-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index e7f86ce..66d98ed 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -38,7 +38,15 @@ chip soc/intel/baytrail
 		device pci 1e.3 off end # HSUART1
 		device pci 1e.4 on  end # HSUART2
 		device pci 1e.5 on  end # SPI
-		device pci 1f.0 on  end # LPC Bridge
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
+				end
+			end
+		end # LPC Bridge
 		device pci 1f.3 off end # SMBus
 	end
 end
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index b16a9cf..a3a1a22 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -321,7 +321,7 @@ static struct device_operations device_ops = {
 	.enable_resources	= NULL,
 	.init			= NULL,
 	.enable			= southcluster_enable_dev,
-	.scan_bus		= NULL,
+	.scan_bus		= scan_static_bus,
 	.ops_pci		= &soc_pci_ops,
 };
 



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