[coreboot-gerrit] Patch set updated for coreboot: 60c31a4 baytrail: use version 2 of efi wrapper

Aaron Durbin (adurbin@google.com) gerrit at coreboot.org
Tue Jan 28 05:41:20 CET 2014


Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4903

-gerrit

commit 60c31a496c21e9c7bf55f0f75ff6069c48a66c32
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Oct 28 09:54:22 2013 -0500

    baytrail: use version 2 of efi wrapper
    
    Version 2 of the efi wrapper wants the speed of the TSC
    timer initialized in the parameter structure.
    
    BUG=chrome-os-partner:22866
    BRANCH=None
    TEST=Built and booted through depthcharge. No errors spit out by
         wrapper.
    CQ-DEPEND=CL:*147256
    
    Change-Id: I9cd265ea6bde93be85fc6fbc905d83af57fc2773
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174712
    Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/baytrail/baytrail/efi_wrapper.h | 4 +++-
 src/soc/intel/baytrail/refcode.c              | 2 ++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/baytrail/baytrail/efi_wrapper.h b/src/soc/intel/baytrail/baytrail/efi_wrapper.h
index 6682f95..3304d03 100644
--- a/src/soc/intel/baytrail/baytrail/efi_wrapper.h
+++ b/src/soc/intel/baytrail/baytrail/efi_wrapper.h
@@ -29,7 +29,7 @@
 #ifndef __EFI_WRAPPER_H__
 #define __EFI_WRAPPER_H__
 
-#define EFI_WRAPPER_VER 1
+#define EFI_WRAPPER_VER 2
 
 /* Provide generic x86 calling conventions. */
 #define ABI_X86 __attribute((regparm(0)))
@@ -44,6 +44,8 @@ struct efi_wrapper_params {
 	int version;
 
 	void ABI_X86 (*console_out)(unsigned char byte);
+
+	unsigned int tsc_ticks_per_microsecond;
 } __attribute__((packed));
 
 typedef int ABI_X86 (*efi_wrapper_entry_t)(struct efi_wrapper_params *);
diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c
index 59e3c4c..7fe7cd4 100644
--- a/src/soc/intel/baytrail/refcode.c
+++ b/src/soc/intel/baytrail/refcode.c
@@ -19,6 +19,7 @@
 
 #include <cbmem.h>
 #include <console/console.h>
+#include <cpu/x86/tsc.h>
 #include <rmodule.h>
 
 #include <baytrail/ramstage.h>
@@ -47,6 +48,7 @@ void baytrail_run_reference_code(void)
 		return;
 	}
 
+	wrp.tsc_ticks_per_microsecond = tsc_freq_mhz();
 	entry = refcode.entry;
 
 	/* Call into reference code. */



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