[coreboot-gerrit] Patch merged into coreboot/master: 47c1725 x86/mtrr: don't assume size of ROM cached during CAR mode

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 47c1725d496c0245abd6534e3d3395bfadc348f9
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Jan 27 16:39:17 2014 -0600

    x86/mtrr: don't assume size of ROM cached during CAR mode
    
    Romstage and ramstage can use 2 different values for the
    amount of ROM to cache just under 4GiB in the address
    space. Don't assume a cpu's romstage caching policy
    for the ROM.
    
    Change-Id: I689fdf4d1f78e9556b0bc258e05c7b9bb99c48e1
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/4846 for details.

-gerrit