[coreboot-gerrit] Patch set updated for coreboot: f92d977 amd/cimx: fix sb(8|9)00 NULL type redefine

Aaron Durbin (adurbin@google.com) gerrit at coreboot.org
Fri Jan 31 05:38:03 CET 2014


Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5088

-gerrit

commit f92d9772e62cf5681617dbfcbff4095650c7904a
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Jan 30 22:20:01 2014 -0600

    amd/cimx: fix sb(8|9)00 NULL type redefine
    
    It is inappropriate for chipset code to be redefining
    types -- especially NULL to a non-pointer type.
    
    Change-Id: Iab5733e5a573baba6fec94e0c955ba4fad72c836
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 6 +-----
 src/southbridge/amd/cimx/sb900/SbPlatform.h | 6 +-----
 src/southbridge/amd/cimx/sb900/cfg.c        | 6 +++---
 src/vendorcode/amd/cimx/sb800/AZALIA.c      | 3 ++-
 4 files changed, 7 insertions(+), 14 deletions(-)

diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
index fa7d196..ea3f719 100644
--- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
@@ -24,11 +24,7 @@
 #ifndef  _AMD_SBPLATFORM_H_
 #define  _AMD_SBPLATFORM_H_
 
-//#include "cbtypes.h"
-#ifdef NULL
-  #undef NULL
-#endif
-#define NULL            0
+#include <stddef.h>
 
 typedef unsigned long long PLACEHOLDER;
 
diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h
index 5e41978..176ad87 100644
--- a/src/southbridge/amd/cimx/sb900/SbPlatform.h
+++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h
@@ -24,11 +24,7 @@
 #ifndef  _AMD_SBPLATFORM_H_
 #define  _AMD_SBPLATFORM_H_
 
-//#include "cbtypes.h"
-#ifdef NULL
-  #undef NULL
-#endif
-#define NULL            0
+#include <stddef.h>
 
 typedef unsigned long long PLACEHOLDER;
 
diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c
index 58c0abe..f37d642 100644
--- a/src/southbridge/amd/cimx/sb900/cfg.c
+++ b/src/southbridge/amd/cimx/sb900/cfg.c
@@ -178,7 +178,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config)
 	// sb_config->HpetMsiDis							= 0;								// Field Retired
 	// sb_config->ResetCpuOnSyncFlood					= 0;								// Field Retired
 	// sb_config->PcibAutoClkCtr						= 0;								// Field Retired
-	sb_config->OEMPROGTBL.OemProgrammingTablePtr	= NULL;							// Board Level
+	sb_config->OEMPROGTBL.OemProgrammingTablePtr	= (typeof(sb_config->OEMPROGTBL.OemProgrammingTablePtr))NULL;							// Board Level
 	sb_config->PORTCONFIG[0].PortCfg.PortPresent	= SB_GPP_PORT0;					// Board Level
 	sb_config->PORTCONFIG[0].PortCfg.PortDetected	= 0;							// CIMx Internal Used
 	sb_config->PORTCONFIG[0].PortCfg.PortIsGen2		= 0;							// CIMx Internal Used
@@ -213,7 +213,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config)
 	sb_config->GppHardwareDowngrade					= INCHIP_GPP_HARDWARE_DOWNGRADE;// Internal Option
 	sb_config->GppToggleReset						= INCHIP_GPP_TOGGLE_RESET;		// External Option
 	sb_config->sdbEnable							= 0;							// CIMx Internal Used
-	sb_config->TempMMIO								= NULL;							// CIMx Internal Used
+	sb_config->TempMMIO								= (typeof(sb_config->TempMMIO))NULL;							// CIMx Internal Used
 	// sb_config->GecPhyStatus							= INCHIP_GEC_PHY_STATUS;		// Field Retired
 	sb_config->SBGecPwr								= INCHIP_GEC_POWER_POLICY;		// Internal Option
 	sb_config->SBGecDebugBus						= INCHIP_GEC_DEBUGBUS;			// Internal Option
@@ -296,7 +296,7 @@ void SbPowerOnInit_Config(AMDSBCFG *sb_config)
     sb_config->SATAMODE.SataMode.SataClkMode		= SATA_CLK_RESERVED;			// Internal Option
     sb_config->NbSbGen2								= NB_SB_GEN2;					// External Option
     sb_config->SataInternal100Spread				= INCHIP_SATA_INTERNAL_100_SPREAD;	// External Option
-    sb_config->OEMPROGTBL.OemProgrammingTablePtr	= NULL;							// Board Level
+    sb_config->OEMPROGTBL.OemProgrammingTablePtr	= (typeof(sb_config->OEMPROGTBL.OemProgrammingTablePtr))NULL;							// Board Level
     sb_config->sdbEnable							= 0;							// CIMx Internal Used
     sb_config->Cg2Pll								= INCHIP_CG2_PLL;				// Internal Option
 
diff --git a/src/vendorcode/amd/cimx/sb800/AZALIA.c b/src/vendorcode/amd/cimx/sb800/AZALIA.c
index edd335f..ec7329a 100644
--- a/src/vendorcode/amd/cimx/sb800/AZALIA.c
+++ b/src/vendorcode/amd/cimx/sb800/AZALIA.c
@@ -284,7 +284,8 @@ azaliaInitAfterPciEnum (
 
   if ( pConfig->AzaliaController != 1 ) {
     RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1);
-    if ( pConfig->BuildParameters.AzaliaSsid != NULL ) {
+    if ( pConfig->BuildParameters.AzaliaSsid !=
+         (typeof(pConfig->BuildParameters.AzaliaSsid))NULL ) {
       RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid);
     } 
     ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);



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