[coreboot-gerrit] New patch to review for coreboot: 434c7b5 vendorcode/amd/agesa/f15tn: Fix erratum #712
Rudolf Marek (r.marek@assembler.cz)
gerrit at coreboot.org
Mon Jul 7 22:39:10 CEST 2014
Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6216
-gerrit
commit 434c7b5644a2b366233b91a31e8f2ad5d85415da
Author: Rudolf Marek <r.marek at assembler.cz>
Date: Mon Jul 7 22:16:36 2014 +0200
vendorcode/amd/agesa/f15tn: Fix erratum #712
Implement the fix for the erratum #712. - Processor May Hang During Graphics Memory Controller
Sequencing
The processor may hang during a graphics memory controller (GMC) sleep state transitioning. The failure may
be processor specific and may be sensitive to temperature.
Potential Effect on System:
System hang.
Suggested Workaround:
BIOS should set D18F2x408_dct[1:0] bit 31 = 1b.
See Publication # 48931 Revision: 3.08
Change-Id: I4346fd4ef3cf554ffdaaad5ab6fc84e73532e885
Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
.../f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c | 52 ++++++++++++++++++++++
.../Proc/CPU/Family/0x15/TN/cpuF15TnPowerMgmt.h | 3 +-
2 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c
index be40b83..59fe8c1 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c
@@ -85,6 +85,13 @@ Erratum687Workaround (
IN AMD_CONFIG_PARAMS *StdHeader
);
+VOID
+STATIC
+Erratum712Workaround (
+ IN UINT32 Data,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
@@ -726,6 +733,18 @@ STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15TnPciWork
0x00000000, // data
}}
},
+ {
+ FamSpecificWorkaround,
+ {
+ (AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily
+ AMD_F15_TN_ALL // CpuRevision
+ },
+ {AMD_PF_ALL}, // platformFeatures
+ {{
+ Erratum712Workaround, // function call
+ 0x00000000, // data
+ }}
+ },
};
@@ -819,4 +838,37 @@ Erratum687Workaround (
LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader);
}
}
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Workaround for Erratum #712 for TN processors.
+ *
+ * AGESA should program D18F2x408_dct[1:0] bit 31 = 1b for all TN parts.
+ *
+ * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched.
+ * @param[in] StdHeader Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+Erratum712Workaround (
+ IN UINT32 Data,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ PCI_ADDR PciAddress;
+ GMC_TO_DCT_CTL_2_REGISTER GmcToDctCtrl2;
+ UINT32 DctSelCnt;
+ DCT_CFG_SEL_REGISTER DctCfgSel;
+ for (DctSelCnt = 0; DctSelCnt <= 1; DctSelCnt++) {
+ PciAddress.AddressValue = GMC_TO_DCT_CTL_2_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader);
+ GmcToDctCtrl2.DisHalfNclkPwrGate |= 1;
+ LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader);
+
+ PciAddress.AddressValue = DCT_CFG_SEL_REG_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader);
+ DctCfgSel.DctCfgSel = ~DctCfgSel.DctCfgSel;
+ LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader);
+ }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerMgmt.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerMgmt.h
index 8740e69..bf5fc64 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerMgmt.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerMgmt.h
@@ -243,7 +243,8 @@ typedef struct {
/// GMC to DCT Control 2 PCI Register
typedef struct {
UINT32 CpuElevPrioDis:1; ///< Cpu elevate priority disable
- UINT32 :31; ///< Reserved
+ UINT32 Reserved_30_1:30; ///<
+ UINT32 DisHalfNclkPwrGate:1; ///<
} GMC_TO_DCT_CTL_2_REGISTER;
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