[coreboot-gerrit] New patch to review for coreboot: 8e7c245 AGESA hudson: Fix SPI writes

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Tue Jul 15 01:36:44 CEST 2014


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6273

-gerrit

commit 8e7c245536e79e7304fa7ef3b1b1a24eaa5fe556
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Tue Jul 15 02:30:49 2014 +0300

    AGESA hudson: Fix SPI writes
    
    Only yangtze has longer FIFO in SPI controller. This was overlooked
    in commit
    
       9f0a2be AMD SPI: Optimise for longer writes
    
    which broke SPI writes and caused CBFS errors with fam15tn.
    
    Change-Id: I821e3f1fa186d2383b30eab9c5d52797c2ef22c5
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/southbridge/amd/agesa/hudson/Kconfig | 5 -----
 src/southbridge/amd/agesa/hudson/spi.c   | 4 ++++
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig
index a0c68a3..9652a8d 100644
--- a/src/southbridge/amd/agesa/hudson/Kconfig
+++ b/src/southbridge/amd/agesa/hudson/Kconfig
@@ -224,11 +224,6 @@ config HUDSON_LEGACY_FREE
 endif # SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
 
 if SOUTHBRIDGE_AMD_AGESA_YANGTZE
-	config AMD_SB_SPI_TX_LEN
-		int
-		default 64
-		depends on SPI_FLASH
-
 	config AZ_PIN
 		hex
 		default 0xaa
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index 2aeb2c0..bbf6dd3 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -43,7 +43,11 @@ static int bus_claimed = 0;
 #define SPI_REG_CNTRL11		0xd
  #define CNTRL11_FIFOPTR_MASK	0x07
 
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
 #define AMD_SB_SPI_TX_LEN	64
+#else
+#define AMD_SB_SPI_TX_LEN	8
+#endif
 
 static u32 spibar;
 



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