[coreboot-gerrit] New patch to review for coreboot: bb9fbd2 Remove a trailing whitespace
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Sun Jul 20 19:24:42 CEST 2014
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6308
-gerrit
commit bb9fbd2d162c46976fe00c6801226a75b0eeaef3
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Sun Jul 20 19:25:05 2014 +0200
Remove a trailing whitespace
Change-Id: I14a9dc99acb5d5365a3d7e99a3964120bb611b05
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
Makefile.inc | 2 +-
payloads/coreinfo/util/kconfig/gconf.c | 2 +-
.../curses/PDCurses-3.4/pdcurses/addchstr.c | 4 +-
.../curses/PDCurses-3.4/pdcurses/addstr.c | 8 +--
.../curses/PDCurses-3.4/pdcurses/inchstr.c | 4 +-
.../curses/PDCurses-3.4/pdcurses/insstr.c | 8 +--
.../curses/PDCurses-3.4/pdcurses/instr.c | 16 ++---
payloads/libpayload/curses/PDCurses-3.4/x11/x11.c | 8 +--
payloads/libpayload/util/kconfig/gconf.c | 2 +-
src/arch/armv7/div0.c | 2 +-
src/cpu/amd/car/post_cache_as_ram.c | 2 +-
src/cpu/amd/geode_gx2/cpubug.c | 2 +-
src/cpu/amd/geode_lx/cpubug.c | 2 +-
src/cpu/amd/model_10xxx/fidvid.c | 16 ++---
src/cpu/amd/quadcore/quadcore.c | 2 +-
src/cpu/amd/sc520/raminit.c | 6 +-
src/cpu/via/nano/nano_init.c | 2 +-
src/device/oprom/x86emu/debug.c | 2 +-
src/device/oprom/x86emu/ops.c | 6 +-
src/device/oprom/x86emu/sys.c | 12 ++--
src/device/oprom/yabel/device.c | 6 +-
src/device/oprom/yabel/interrupt.c | 2 +-
src/device/oprom/yabel/vbe.c | 2 +-
src/drivers/i2c/w83795/w83795.c | 2 +-
src/drivers/intel/gma/intel_ddi.c | 2 +-
src/drivers/intel/gma/intel_dp.c | 2 +-
src/lib/libgcov.c | 2 +-
src/mainboard/advansus/a785e-i/romstage.c | 10 +--
src/mainboard/amd/bimini_fam10/romstage.c | 10 +--
src/mainboard/amd/dinar/romstage.c | 4 +-
src/mainboard/amd/inagua/romstage.c | 4 +-
src/mainboard/amd/mahogany_fam10/romstage.c | 10 +--
src/mainboard/amd/olivehill/romstage.c | 4 +-
src/mainboard/amd/parmer/romstage.c | 4 +-
src/mainboard/amd/persimmon/romstage.c | 4 +-
src/mainboard/amd/serengeti_cheetah/irq_tables.c | 4 +-
.../amd/serengeti_cheetah_fam10/romstage.c | 12 ++--
src/mainboard/amd/south_station/romstage.c | 4 +-
src/mainboard/amd/thatcher/romstage.c | 4 +-
src/mainboard/amd/tilapia_fam10/romstage.c | 10 +--
src/mainboard/amd/torpedo/romstage.c | 4 +-
src/mainboard/amd/union_station/romstage.c | 4 +-
src/mainboard/arima/hdama/mptable.c | 4 +-
src/mainboard/artecgroup/dbe61/romstage.c | 6 +-
src/mainboard/asrock/e350m1/romstage.c | 4 +-
src/mainboard/asrock/imb-a180/romstage.c | 4 +-
src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +-
src/mainboard/asus/a8v-e_se/romstage.c | 2 +-
src/mainboard/asus/f2a85-m/romstage.c | 4 +-
src/mainboard/asus/k8v-x/romstage.c | 2 +-
src/mainboard/asus/m2v-mx_se/romstage.c | 4 +-
src/mainboard/asus/m2v/romstage.c | 2 +-
src/mainboard/asus/m4a78-em/romstage.c | 10 +--
src/mainboard/asus/m4a785-m/romstage.c | 10 +--
src/mainboard/asus/m5a88-v/romstage.c | 10 +--
src/mainboard/avalue/eax-785e/romstage.c | 10 +--
src/mainboard/gigabyte/ma785gm/romstage.c | 10 +--
src/mainboard/gigabyte/ma785gmt/romstage.c | 10 +--
src/mainboard/gigabyte/ma78gm/romstage.c | 10 +--
src/mainboard/gizmosphere/gizmo/romstage.c | 4 +-
src/mainboard/hp/dl145_g3/mptable.c | 2 +-
src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 4 +-
src/mainboard/iei/kino-780am2-fam10/romstage.c | 10 +--
src/mainboard/iwave/iWRainbowG6/romstage.c | 2 +-
src/mainboard/iwill/dk8_htx/irq_tables.c | 4 +-
src/mainboard/jetway/nf81-t56n-lf/romstage.c | 4 +-
src/mainboard/jetway/pa78vm5/romstage.c | 10 +--
src/mainboard/lippert/frontrunner-af/romstage.c | 4 +-
src/mainboard/lippert/toucan-af/romstage.c | 4 +-
src/mainboard/supermicro/h8dmr_fam10/romstage.c | 10 +--
src/mainboard/supermicro/h8qgi/agesawrapper.c | 4 +-
src/mainboard/supermicro/h8qgi/romstage.c | 4 +-
src/mainboard/supermicro/h8qme_fam10/romstage.c | 10 +--
src/mainboard/supermicro/h8scm/agesawrapper.c | 4 +-
src/mainboard/supermicro/h8scm/romstage.c | 4 +-
src/mainboard/supermicro/h8scm_fam10/romstage.c | 10 +--
src/mainboard/tyan/s2882/irq_tables.c | 6 +-
src/mainboard/tyan/s8226/agesawrapper.c | 4 +-
src/mainboard/tyan/s8226/romstage.c | 4 +-
src/mainboard/via/epia-m700/romstage.c | 4 +-
src/mainboard/via/epia-m850/romstage.c | 2 +-
src/northbridge/amd/amdfam10/raminit_amdmct.c | 2 +-
src/northbridge/amd/amdmct/mct/mct_d.c | 6 +-
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 +-
src/northbridge/amd/amdmct/wrappers/mcti_d.c | 2 +-
src/northbridge/intel/i945/raminit.c | 12 ++--
src/northbridge/intel/sch/raminit.c | 2 +-
src/northbridge/via/vx800/examples/chipset_init.c | 10 +--
src/northbridge/via/vx800/examples/romstage.c | 4 +-
src/northbridge/via/vx900/northbridge.c | 4 +-
src/southbridge/amd/amd8132/bridge.c | 2 +-
src/southbridge/amd/rs780/gfx.c | 80 +++++++++++-----------
src/southbridge/nvidia/ck804/lpc.c | 2 +-
src/southbridge/nvidia/ck804/sata.c | 2 +-
src/southbridge/nvidia/mcp55/sata.c | 4 +-
src/southbridge/ricoh/rl5c476/rl5c476.c | 2 +-
src/southbridge/sis/sis966/aza.c | 2 +-
src/southbridge/sis/sis966/nic.c | 6 +-
src/southbridge/ti/pci7420/cardbus.c | 4 +-
src/southbridge/ti/pcixx12/pcixx12.c | 4 +-
.../amd/agesa/f10/Proc/Common/S3RestoreState.c | 2 +-
.../amd/agesa/f10/Proc/Mem/Ps/HY/mprhy3.c | 8 +--
.../amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.c | 2 +-
.../amd/agesa/f12/Proc/Common/S3RestoreState.c | 2 +-
.../amd/agesa/f12/Proc/Common/S3SaveState.c | 2 +-
.../amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c | 2 +-
.../amd/agesa/f12/Proc/Fch/Interface/FchInitLate.c | 2 +-
.../amd/agesa/f12/Proc/Fch/Interface/FchInitMid.c | 2 +-
.../amd/agesa/f12/Proc/Fch/Sata/SataLib.c | 2 +-
.../Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c | 2 +-
.../Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c | 6 +-
.../agesa/f12/Proc/GNB/Nb/Family/LN/F12NbLclkDpm.c | 2 +-
.../agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.c | 8 +--
.../amd/agesa/f12/Proc/Mem/Main/mmLvDdr3.c | 2 +-
src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mndct.c | 2 +-
.../amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.c | 2 +-
.../amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c | 2 +-
.../amd/agesa/f14/Proc/Common/S3RestoreState.c | 2 +-
.../amd/agesa/f14/Proc/Common/S3SaveState.c | 2 +-
.../Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c | 2 +-
.../f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c | 2 +-
.../agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c | 6 +-
.../amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c | 2 +-
.../amd/agesa/f15/Proc/Common/S3RestoreState.c | 2 +-
.../amd/agesa/f15/Proc/Common/S3SaveState.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.c | 2 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mndct.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c | 2 +-
.../amd/agesa/f15/Proc/Mem/Tech/mtthrcSeedTrain.c | 2 +-
.../amd/agesa/f15tn/Proc/Common/S3RestoreState.c | 2 +-
.../amd/agesa/f15tn/Proc/Common/S3SaveState.c | 2 +-
.../agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c | 2 +-
.../agesa/f15tn/Proc/Fch/Interface/FchInitLate.c | 2 +-
.../agesa/f15tn/Proc/Fch/Interface/FchInitMid.c | 2 +-
.../amd/agesa/f15tn/Proc/Fch/Sata/SataLib.c | 2 +-
.../Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c | 10 +--
.../Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c | 2 +-
.../Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c | 6 +-
.../amd/agesa/f15tn/Proc/Mem/Main/mmLvDdr3.c | 2 +-
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c | 2 +-
.../amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c | 2 +-
.../agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c | 2 +-
.../amd/agesa/f16kb/Proc/Common/S3RestoreState.c | 2 +-
.../amd/agesa/f16kb/Proc/Common/S3SaveState.c | 2 +-
.../agesa/f16kb/Proc/Fch/Interface/FchInitEnv.c | 2 +-
.../agesa/f16kb/Proc/Fch/Interface/FchInitLate.c | 2 +-
.../agesa/f16kb/Proc/Fch/Interface/FchInitMid.c | 2 +-
.../amd/agesa/f16kb/Proc/Fch/Sata/SataLib.c | 2 +-
.../GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c | 12 ++--
.../f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c | 2 +-
.../Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c | 2 +-
.../Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c | 8 +--
.../amd/agesa/f16kb/Proc/Mem/Main/mmLvDdr3.c | 2 +-
.../amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c | 2 +-
.../f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c | 2 +-
.../agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c | 12 ++--
.../agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c | 2 +-
src/vendorcode/amd/cimx/rd890/nbDispatcher.c | 4 +-
src/vendorcode/amd/cimx/rd890/nbIoApic.c | 2 +-
src/vendorcode/amd/cimx/rd890/nbIommu.c | 2 +-
src/vendorcode/amd/cimx/rd890/nbLib.c | 4 +-
src/vendorcode/amd/cimx/rd890/nbPcieAspm.c | 2 +-
src/vendorcode/amd/cimx/rd890/nbPcieInitEarly.c | 4 +-
src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c | 4 +-
src/vendorcode/amd/cimx/rd890/nbPcieLateHwLib.c | 2 +-
src/vendorcode/amd/cimx/rd890/nbPcieLib.c | 4 +-
src/vendorcode/amd/cimx/rd890/nbPciePllControl.c | 2 +-
src/vendorcode/amd/cimx/rd890/nbPciePortRemap.c | 4 +-
src/vendorcode/amd/cimx/sb700/AZALIA.c | 12 ++--
src/vendorcode/amd/cimx/sb700/FLASH.c | 2 +-
src/vendorcode/amd/cimx/sb700/SATA.c | 4 +-
src/vendorcode/amd/cimx/sb700/SBCMN.c | 6 +-
src/vendorcode/amd/cimx/sb700/SBMAIN.c | 14 ++--
src/vendorcode/amd/cimx/sb700/SBPOR.c | 2 +-
src/vendorcode/amd/cimx/sb700/SMM.c | 8 +--
src/vendorcode/amd/cimx/sb700/USB.c | 2 +-
src/vendorcode/amd/cimx/sb900/Azalia.c | 12 ++--
src/vendorcode/amd/cimx/sb900/Sata.c | 6 +-
src/vendorcode/amd/cimx/sb900/SbCmn.c | 6 +-
src/vendorcode/amd/cimx/sb900/SbMain.c | 18 ++---
src/vendorcode/amd/cimx/sb900/SbPor.c | 2 +-
src/vendorcode/amd/cimx/sb900/Smm.c | 6 +-
src/vendorcode/amd/cimx/sb900/Usb.c | 2 +-
util/abuild/abuild | 2 +-
util/crossgcc/buildgcc | 4 +-
util/kconfig/gconf.c | 2 +-
util/kconfig/nconf.c | 2 +-
util/mkelfImage/linux-ia64/convert_params.c | 2 +-
util/mkelfImage/main/mkelfImage.c | 2 +-
util/mptable/mptable.c | 2 +-
util/msrtool/sys.c | 12 ++--
util/optionlist/kconfig2wiki | 2 +-
util/romcc/romcc.c | 6 +-
util/vgabios/testbios.c | 4 +-
194 files changed, 468 insertions(+), 468 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index 42ed707..944d332 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -529,7 +529,7 @@ ifeq ($(CONFIG_PXE_ROM),y)
endif
ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
ifeq ($(CONFIG_CPU_MICROCODE_IN_CBFS),y)
- @printf " UPDATE-FIT \n"
+ @printf " UPDATE-FIT\n"
$(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES)
endif
endif
diff --git a/payloads/coreinfo/util/kconfig/gconf.c b/payloads/coreinfo/util/kconfig/gconf.c
index 93d9670..945e421 100644
--- a/payloads/coreinfo/util/kconfig/gconf.c
+++ b/payloads/coreinfo/util/kconfig/gconf.c
@@ -749,7 +749,7 @@ void on_introduction1_activate(GtkMenuItem * menuitem, gpointer user_data)
"are interested in, you can still view the help of a grayed-out\n"
"option.\n"
"\n"
- "Toggling Show Debug Info under the Options menu will show \n"
+ "Toggling Show Debug Info under the Options menu will show\n"
"the dependencies, which you can then match by examining other options.");
dialog = gtk_message_dialog_new(GTK_WINDOW(main_wnd),
diff --git a/payloads/libpayload/curses/PDCurses-3.4/pdcurses/addchstr.c b/payloads/libpayload/curses/PDCurses-3.4/pdcurses/addchstr.c
index 249ea8d..b03bcd5 100644
--- a/payloads/libpayload/curses/PDCurses-3.4/pdcurses/addchstr.c
+++ b/payloads/libpayload/curses/PDCurses-3.4/pdcurses/addchstr.c
@@ -163,7 +163,7 @@ int mvwaddchstr(WINDOW *win, int y, int x, const chtype *ch)
int mvwaddchnstr(WINDOW *win, int y, int x, const chtype *ch, int n)
{
- PDC_LOG(("mvwaddchnstr() - called: y %d x %d n %d \n", y, x, n));
+ PDC_LOG(("mvwaddchnstr() - called: y %d x %d n %d\n", y, x, n));
if (wmove(win, y, x) == ERR)
return ERR;
@@ -232,7 +232,7 @@ int mvwadd_wchstr(WINDOW *win, int y, int x, const cchar_t *wch)
int mvwadd_wchnstr(WINDOW *win, int y, int x, const cchar_t *wch, int n)
{
- PDC_LOG(("mvwadd_wchnstr() - called: y %d x %d n %d \n", y, x, n));
+ PDC_LOG(("mvwadd_wchnstr() - called: y %d x %d n %d\n", y, x, n));
if (wmove(win, y, x) == ERR)
return ERR;
diff --git a/payloads/libpayload/curses/PDCurses-3.4/pdcurses/addstr.c b/payloads/libpayload/curses/PDCurses-3.4/pdcurses/addstr.c
index ca19fd0..a828aaa 100644
--- a/payloads/libpayload/curses/PDCurses-3.4/pdcurses/addstr.c
+++ b/payloads/libpayload/curses/PDCurses-3.4/pdcurses/addstr.c
@@ -65,7 +65,7 @@ int waddnstr(WINDOW *win, const char *str, int n)
{
int i = 0;
- PDC_LOG(("waddnstr() - called: string=\"%s\" n %d \n", str, n));
+ PDC_LOG(("waddnstr() - called: string=\"%s\" n %d\n", str, n));
if (!win || !str)
return ERR;
@@ -99,7 +99,7 @@ int addstr(const char *str)
int addnstr(const char *str, int n)
{
- PDC_LOG(("addnstr() - called: string=\"%s\" n %d \n", str, n));
+ PDC_LOG(("addnstr() - called: string=\"%s\" n %d\n", str, n));
return waddnstr(stdscr, str, n);
}
@@ -123,7 +123,7 @@ int mvaddstr(int y, int x, const char *str)
int mvaddnstr(int y, int x, const char *str, int n)
{
- PDC_LOG(("mvaddnstr() - called: y %d x %d string=\"%s\" n %d \n",
+ PDC_LOG(("mvaddnstr() - called: y %d x %d string=\"%s\" n %d\n",
y, x, str, n));
if (move(y, x) == ERR)
@@ -144,7 +144,7 @@ int mvwaddstr(WINDOW *win, int y, int x, const char *str)
int mvwaddnstr(WINDOW *win, int y, int x, const char *str, int n)
{
- PDC_LOG(("mvwaddnstr() - called: y %d x %d string=\"%s\" n %d \n",
+ PDC_LOG(("mvwaddnstr() - called: y %d x %d string=\"%s\" n %d\n",
y, x, str, n));
if (wmove(win, y, x) == ERR)
diff --git a/payloads/libpayload/curses/PDCurses-3.4/pdcurses/inchstr.c b/payloads/libpayload/curses/PDCurses-3.4/pdcurses/inchstr.c
index f061cdb..c0461ba 100644
--- a/payloads/libpayload/curses/PDCurses-3.4/pdcurses/inchstr.c
+++ b/payloads/libpayload/curses/PDCurses-3.4/pdcurses/inchstr.c
@@ -132,7 +132,7 @@ int mvinchnstr(int y, int x, chtype *ch, int n)
int mvwinchnstr(WINDOW *win, int y, int x, chtype *ch, int n)
{
- PDC_LOG(("mvwinchnstr() - called: y %d x %d n %d \n", y, x, n));
+ PDC_LOG(("mvwinchnstr() - called: y %d x %d n %d\n", y, x, n));
if (wmove(win, y, x) == ERR)
return ERR;
@@ -201,7 +201,7 @@ int mvin_wchnstr(int y, int x, cchar_t *wch, int n)
int mvwin_wchnstr(WINDOW *win, int y, int x, cchar_t *wch, int n)
{
- PDC_LOG(("mvwinchnstr() - called: y %d x %d n %d \n", y, x, n));
+ PDC_LOG(("mvwinchnstr() - called: y %d x %d n %d\n", y, x, n));
if (wmove(win, y, x) == ERR)
return ERR;
diff --git a/payloads/libpayload/curses/PDCurses-3.4/pdcurses/insstr.c b/payloads/libpayload/curses/PDCurses-3.4/pdcurses/insstr.c
index a731eaf..1d18e02 100644
--- a/payloads/libpayload/curses/PDCurses-3.4/pdcurses/insstr.c
+++ b/payloads/libpayload/curses/PDCurses-3.4/pdcurses/insstr.c
@@ -73,7 +73,7 @@ int winsnstr(WINDOW *win, const char *str, int n)
#endif
int len;
- PDC_LOG(("winsnstr() - called: string=\"%s\" n %d \n", str, n));
+ PDC_LOG(("winsnstr() - called: string=\"%s\" n %d\n", str, n));
if (!win || !str)
return ERR;
@@ -147,14 +147,14 @@ int mvwinsstr(WINDOW *win, int y, int x, const char *str)
int insnstr(const char *str, int n)
{
- PDC_LOG(("insnstr() - called: string=\"%s\" n %d \n", str, n));
+ PDC_LOG(("insnstr() - called: string=\"%s\" n %d\n", str, n));
return winsnstr(stdscr, str, n);
}
int mvinsnstr(int y, int x, const char *str, int n)
{
- PDC_LOG(("mvinsnstr() - called: y %d x %d string=\"%s\" n %d \n",
+ PDC_LOG(("mvinsnstr() - called: y %d x %d string=\"%s\" n %d\n",
y, x, str, n));
if (move(y, x) == ERR)
@@ -165,7 +165,7 @@ int mvinsnstr(int y, int x, const char *str, int n)
int mvwinsnstr(WINDOW *win, int y, int x, const char *str, int n)
{
- PDC_LOG(("mvwinsnstr() - called: y %d x %d string=\"%s\" n %d \n",
+ PDC_LOG(("mvwinsnstr() - called: y %d x %d string=\"%s\" n %d\n",
y, x, str, n));
if (wmove(win, y, x) == ERR)
diff --git a/payloads/libpayload/curses/PDCurses-3.4/pdcurses/instr.c b/payloads/libpayload/curses/PDCurses-3.4/pdcurses/instr.c
index 733a348..42c5c19 100644
--- a/payloads/libpayload/curses/PDCurses-3.4/pdcurses/instr.c
+++ b/payloads/libpayload/curses/PDCurses-3.4/pdcurses/instr.c
@@ -76,7 +76,7 @@ int winnstr(WINDOW *win, char *str, int n)
chtype *src;
int i;
- PDC_LOG(("winnstr() - called: n %d \n", n));
+ PDC_LOG(("winnstr() - called: n %d\n", n));
if (!win || !str)
return ERR;
@@ -104,14 +104,14 @@ int instr(char *str)
int winstr(WINDOW *win, char *str)
{
- PDC_LOG(("winstr() - called: \n"));
+ PDC_LOG(("winstr() - called:\n"));
return (ERR == winnstr(win, str, win->_maxx)) ? ERR : OK;
}
int mvinstr(int y, int x, char *str)
{
- PDC_LOG(("mvinstr() - called: y %d x %d \n", y, x));
+ PDC_LOG(("mvinstr() - called: y %d x %d\n", y, x));
if (move(y, x) == ERR)
return ERR;
@@ -121,7 +121,7 @@ int mvinstr(int y, int x, char *str)
int mvwinstr(WINDOW *win, int y, int x, char *str)
{
- PDC_LOG(("mvwinstr() - called: y %d x %d \n", y, x));
+ PDC_LOG(("mvwinstr() - called: y %d x %d\n", y, x));
if (wmove(win, y, x) == ERR)
return ERR;
@@ -131,14 +131,14 @@ int mvwinstr(WINDOW *win, int y, int x, char *str)
int innstr(char *str, int n)
{
- PDC_LOG(("innstr() - called: n %d \n", n));
+ PDC_LOG(("innstr() - called: n %d\n", n));
return winnstr(stdscr, str, n);
}
int mvinnstr(int y, int x, char *str, int n)
{
- PDC_LOG(("mvinnstr() - called: y %d x %d n %d \n", y, x, n));
+ PDC_LOG(("mvinnstr() - called: y %d x %d n %d\n", y, x, n));
if (move(y, x) == ERR)
return ERR;
@@ -148,7 +148,7 @@ int mvinnstr(int y, int x, char *str, int n)
int mvwinnstr(WINDOW *win, int y, int x, char *str, int n)
{
- PDC_LOG(("mvwinnstr() - called: y %d x %d n %d \n", y, x, n));
+ PDC_LOG(("mvwinnstr() - called: y %d x %d n %d\n", y, x, n));
if (wmove(win, y, x) == ERR)
return ERR;
@@ -162,7 +162,7 @@ int winnwstr(WINDOW *win, wchar_t *wstr, int n)
chtype *src;
int i;
- PDC_LOG(("winnstr() - called: n %d \n", n));
+ PDC_LOG(("winnstr() - called: n %d\n", n));
if (!win || !wstr)
return ERR;
diff --git a/payloads/libpayload/curses/PDCurses-3.4/x11/x11.c b/payloads/libpayload/curses/PDCurses-3.4/x11/x11.c
index 69c3199..4817bea 100644
--- a/payloads/libpayload/curses/PDCurses-3.4/x11/x11.c
+++ b/payloads/libpayload/curses/PDCurses-3.4/x11/x11.c
@@ -404,10 +404,10 @@ static XIC Xic = NULL;
static const char *default_translations =
{
- "<Key>: XCursesKeyPress() \n" \
- "<KeyUp>: XCursesKeyPress() \n" \
- "<BtnDown>: XCursesButton() \n" \
- "<BtnUp>: XCursesButton() \n" \
+ "<Key>: XCursesKeyPress()\n" \
+ "<KeyUp>: XCursesKeyPress()\n" \
+ "<BtnDown>: XCursesButton()\n" \
+ "<BtnUp>: XCursesButton()\n" \
"<BtnMotion>: XCursesButton()"
};
diff --git a/payloads/libpayload/util/kconfig/gconf.c b/payloads/libpayload/util/kconfig/gconf.c
index bc9f5ba..79790a6 100644
--- a/payloads/libpayload/util/kconfig/gconf.c
+++ b/payloads/libpayload/util/kconfig/gconf.c
@@ -749,7 +749,7 @@ void on_introduction1_activate(GtkMenuItem * menuitem, gpointer user_data)
"are interested in, you can still view the help of a grayed-out\n"
"option.\n"
"\n"
- "Toggling Show Debug Info under the Options menu will show \n"
+ "Toggling Show Debug Info under the Options menu will show\n"
"the dependencies, which you can then match by examining other options.");
dialog = gtk_message_dialog_new(GTK_WINDOW(main_wnd),
diff --git a/src/arch/armv7/div0.c b/src/arch/armv7/div0.c
index ab06ad3..77e3c37 100644
--- a/src/arch/armv7/div0.c
+++ b/src/arch/armv7/div0.c
@@ -29,5 +29,5 @@ void __div0(void); // called from asm so no need for a prototype in a header
/* recursion is ok here because we have no formats ... */
void __div0 (void)
{
- printk(BIOS_EMERG, "DIVIDE BY ZERO! continuing ... \n");
+ printk(BIOS_EMERG, "DIVIDE BY ZERO! continuing ...\n");
}
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 3a0763a..7965c69 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -120,7 +120,7 @@ cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused)))
/* only global variable sysinfo in cache need to be offset */
print_debug("Done\n");
- print_debug("Disabling cache as ram now \n");
+ print_debug("Disabling cache as ram now\n");
disable_cache_as_ram_bsp();
diff --git a/src/cpu/amd/geode_gx2/cpubug.c b/src/cpu/amd/geode_gx2/cpubug.c
index b6824ad..3e035a6 100644
--- a/src/cpu/amd/geode_gx2/cpubug.c
+++ b/src/cpu/amd/geode_gx2/cpubug.c
@@ -342,5 +342,5 @@ void cpubug(void)
bug784();
bug118253();
disablememoryreadorder();
- printk(BIOS_DEBUG, "Done cpubug fixes \n");
+ printk(BIOS_DEBUG, "Done cpubug fixes\n");
}
diff --git a/src/cpu/amd/geode_lx/cpubug.c b/src/cpu/amd/geode_lx/cpubug.c
index ebadec7..c980629 100644
--- a/src/cpu/amd/geode_lx/cpubug.c
+++ b/src/cpu/amd/geode_lx/cpubug.c
@@ -86,5 +86,5 @@ void cpubug(void)
{
pcideadlock();
disablememoryreadorder();
- printk(BIOS_DEBUG, "Done cpubug fixes \n");
+ printk(BIOS_DEBUG, "Done cpubug fixes\n");
}
diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
index 4297c90..8f5f1cf 100644
--- a/src/cpu/amd/model_10xxx/fidvid.c
+++ b/src/cpu/amd/model_10xxx/fidvid.c
@@ -146,7 +146,7 @@ static void enable_fid_change(u8 fid)
dword |= (u32) fid & 0x1F;
dword |= 1 << 5; // enable
pci_write_config32(dev, 0xd4, dword);
- printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i,
+ printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x\n", i,
dword);
}
}
@@ -590,7 +590,7 @@ static void prep_fid_change(void)
nodes = get_nodes();
for (i = 0; i < nodes; i++) {
- printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i);
+ printk(BIOS_DEBUG, "Prep FID/VID Node:%02x\n", i);
dev = NODE_PCI(i, 3);
u32 cpuRev = mctGetLogicalCPUID(0xFF) ;
u8 procPkg = mctGetProcessorPackageType();
@@ -608,15 +608,15 @@ static void prep_fid_change(void)
config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg);
dword = pci_read_config32(dev, 0x80);
- printk(BIOS_DEBUG, " F3x80: %08x \n", dword);
+ printk(BIOS_DEBUG, " F3x80: %08x\n", dword);
dword = pci_read_config32(dev, 0x84);
- printk(BIOS_DEBUG, " F3x84: %08x \n", dword);
+ printk(BIOS_DEBUG, " F3x84: %08x\n", dword);
dword = pci_read_config32(dev, 0xD4);
- printk(BIOS_DEBUG, " F3xD4: %08x \n", dword);
+ printk(BIOS_DEBUG, " F3xD4: %08x\n", dword);
dword = pci_read_config32(dev, 0xD8);
- printk(BIOS_DEBUG, " F3xD8: %08x \n", dword);
+ printk(BIOS_DEBUG, " F3xD8: %08x\n", dword);
dword = pci_read_config32(dev, 0xDC);
- printk(BIOS_DEBUG, " F3xDC: %08x \n", dword);
+ printk(BIOS_DEBUG, " F3xDC: %08x\n", dword);
}
@@ -737,7 +737,7 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode)
* PstatMaxVal is going to be 0 on cold reset anyway ?
*/
if ( ! (pci_read_config32(dev, 0xDC) & (~ PS_MAX_VAL_MASK)) ) {
- printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1 \n");
+ printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1\n");
};
msr.lo &= ~0xFE000000; // clear nbvid
diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
index feff3e1..26f8036 100644
--- a/src/cpu/amd/quadcore/quadcore.c
+++ b/src/cpu/amd/quadcore/quadcore.c
@@ -91,7 +91,7 @@ static void start_other_cores(void)
for (nodeid = 0; nodeid < nodes; nodeid++) {
u32 cores = get_core_num_in_bsp(nodeid);
- printk(BIOS_DEBUG, "init node: %02x cores: %02x \n", nodeid, cores);
+ printk(BIOS_DEBUG, "init node: %02x cores: %02x\n", nodeid, cores);
if (cores > 0) {
real_start_other_core(nodeid, cores);
}
diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c
index f3f7071..ee3b769 100644
--- a/src/cpu/amd/sc520/raminit.c
+++ b/src/cpu/amd/sc520/raminit.c
@@ -304,7 +304,7 @@ int sizemem(void)
/* issue all banks precharge */
*drcctl=0x02;
- print_err("set *drcctl to 2 \n");
+ print_err("set *drcctl to 2\n");
dummy_write();
print_err("PRE\n");
@@ -337,7 +337,7 @@ int sizemem(void)
for(bank = 3; bank >= 0; bank--) {
print_err("Try to assign to l\n");
*lp = 0xdeadbeef;
- print_err("assigned l ... \n");
+ print_err("assigned l ...\n");
if (*lp != 0xdeadbeef) {
print_err(" no memory at bank ");
// print_err_hex8(bank);
@@ -379,7 +379,7 @@ int sizemem(void)
/* issue all banks precharge */
*drcctl=0x02;
- print_err("set *drcctl to 2 \n");
+ print_err("set *drcctl to 2\n");
dummy_write();
print_err("PRE\n");
diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c
index 417119f..87f08ed 100644
--- a/src/cpu/via/nano/nano_init.c
+++ b/src/cpu/via/nano/nano_init.c
@@ -148,7 +148,7 @@ static void nano_init(device_t dev)
/* We didn't test this on the Nano 1000/2000 series, so warn the user */
if(c.x86_mask < MODEL_NANO_3000_B0) {
printk(BIOS_EMERG, "WARNING: This CPU has not been tested. "
- "Please report any issues encountered. \n");
+ "Please report any issues encountered.\n");
}
switch (c.x86_mask) {
case MODEL_NANO:
diff --git a/src/device/oprom/x86emu/debug.c b/src/device/oprom/x86emu/debug.c
index e7a111b..020353d 100644
--- a/src/device/oprom/x86emu/debug.c
+++ b/src/device/oprom/x86emu/debug.c
@@ -404,7 +404,7 @@ void x86emu_dump_xregs (void)
printf("\tEAX=%08x ", M.x86.R_EAX );
printf("EBX=%08x ", M.x86.R_EBX );
printf("ECX=%08x ", M.x86.R_ECX );
- printf("EDX=%08x \n", M.x86.R_EDX );
+ printf("EDX=%08x\n", M.x86.R_EDX );
printf("\tESP=%08x ", M.x86.R_ESP );
printf("EBP=%08x ", M.x86.R_EBP );
printf("ESI=%08x ", M.x86.R_ESI );
diff --git a/src/device/oprom/x86emu/ops.c b/src/device/oprom/x86emu/ops.c
index c805b58..803e0c6 100644
--- a/src/device/oprom/x86emu/ops.c
+++ b/src/device/oprom/x86emu/ops.c
@@ -4986,7 +4986,7 @@ static void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1))
case 5:
case 6:
case 7:
- DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod);
+ DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x\n", mod);
HALT_SYS();
break;
}
@@ -5183,7 +5183,7 @@ static void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1))
M.x86.R_IP = *destreg;
break;
case 3: /* jmp far ptr ... */
- DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n");
+ DECODE_PRINTF("OPERATION UNDEFINED 0XFF\n");
TRACE_AND_STEP();
HALT_SYS();
break;
@@ -5195,7 +5195,7 @@ static void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1))
M.x86.R_IP = (u16) (*destreg);
break;
case 5: /* jmp far ptr ... */
- DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n");
+ DECODE_PRINTF("OPERATION UNDEFINED 0XFF\n");
TRACE_AND_STEP();
HALT_SYS();
break;
diff --git a/src/device/oprom/x86emu/sys.c b/src/device/oprom/x86emu/sys.c
index 9785a9d..88811d4 100644
--- a/src/device/oprom/x86emu/sys.c
+++ b/src/device/oprom/x86emu/sys.c
@@ -216,7 +216,7 @@ Default PIO byte read function. Doesn't perform real inb.
static u8 X86API p_inb(X86EMU_pioAddr addr)
{
DB(if (DEBUG_IO_TRACE())
- printf("inb %#04x \n", addr);)
+ printf("inb %#04x\n", addr);)
return inb(addr);
}
@@ -231,7 +231,7 @@ Default PIO word read function. Doesn't perform real inw.
static u16 X86API p_inw(X86EMU_pioAddr addr)
{
DB(if (DEBUG_IO_TRACE())
- printf("inw %#04x \n", addr);)
+ printf("inw %#04x\n", addr);)
return inw(addr);
}
@@ -246,7 +246,7 @@ Default PIO long read function. Doesn't perform real inl.
static u32 X86API p_inl(X86EMU_pioAddr addr)
{
DB(if (DEBUG_IO_TRACE())
- printf("inl %#04x \n", addr);)
+ printf("inl %#04x\n", addr);)
return inl(addr);
}
@@ -260,7 +260,7 @@ Default PIO byte write function. Doesn't perform real outb.
static void X86API p_outb(X86EMU_pioAddr addr, u8 val)
{
DB(if (DEBUG_IO_TRACE())
- printf("outb %#02x -> %#04x \n", val, addr);)
+ printf("outb %#02x -> %#04x\n", val, addr);)
outb(val, addr);
return;
}
@@ -275,7 +275,7 @@ Default PIO word write function. Doesn't perform real outw.
static void X86API p_outw(X86EMU_pioAddr addr, u16 val)
{
DB(if (DEBUG_IO_TRACE())
- printf("outw %#04x -> %#04x \n", val, addr);)
+ printf("outw %#04x -> %#04x\n", val, addr);)
outw(val, addr);
return;
}
@@ -290,7 +290,7 @@ Default PIO ;ong write function. Doesn't perform real outl.
static void X86API p_outl(X86EMU_pioAddr addr, u32 val)
{
DB(if (DEBUG_IO_TRACE())
- printf("outl %#08x -> %#04x \n", val, addr);)
+ printf("outl %#08x -> %#04x\n", val, addr);)
outl(val, addr);
return;
diff --git a/src/device/oprom/yabel/device.c b/src/device/oprom/yabel/device.c
index 2f41847..6a74a78 100644
--- a/src/device/oprom/yabel/device.c
+++ b/src/device/oprom/yabel/device.c
@@ -76,7 +76,7 @@ biosemu_dev_get_addr_info(void)
taa_index++;
/* legacy ranges if its a VGA card... */
if ((bios_device.dev->class & 0xFF0000) == 0x030000) {
- DEBUG_PRINTF("%s: VGA device found, adding legacy resources... \n", __func__);
+ DEBUG_PRINTF("%s: VGA device found, adding legacy resources...\n", __func__);
/* I/O 0x3B0-0x3BB */
translate_address_array[taa_index].info = IORESOURCE_FIXED | IORESOURCE_IO;
translate_address_array[taa_index].bus = bus;
@@ -112,7 +112,7 @@ biosemu_dev_get_addr_info(void)
taa_last_entry = taa_index - 1;
#if CONFIG_X86EMU_DEBUG
//dump translate_address_array
- printf("translate_address_array: \n");
+ printf("translate_address_array:\n");
translate_address_t ta;
int i;
for (i = 0; i <= taa_last_entry; i++) {
@@ -196,7 +196,7 @@ biosemu_dev_get_addr_info(void)
taa_last_entry = taa_index - 1;
#if CONFIG_X86EMU_DEBUG
//dump translate_address_array
- printf("translate_address_array: \n");
+ printf("translate_address_array:\n");
translate_address_t ta;
for (i = 0; i <= taa_last_entry; i++) {
ta = translate_address_array[i];
diff --git a/src/device/oprom/yabel/interrupt.c b/src/device/oprom/yabel/interrupt.c
index 92b058b..c3d8b75 100644
--- a/src/device/oprom/yabel/interrupt.c
+++ b/src/device/oprom/yabel/interrupt.c
@@ -365,7 +365,7 @@ handleInt1a(void)
#endif
} else {
DEBUG_PRINTF_INTR
- ("%s(): function %x: invalid device/vendor/device index! (%04x/%04x/%02x expected: %04x/%04x/00) \n",
+ ("%s(): function %x: invalid device/vendor/device index! (%04x/%04x/%02x expected: %04x/%04x/00)\n",
__func__, M.x86.R_AX, M.x86.R_CX, M.x86.R_DX,
M.x86.R_SI, bios_device.pci_device_id,
bios_device.pci_vendor_id);
diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c
index 6283bbb..bb552eb 100644
--- a/src/device/oprom/yabel/vbe.c
+++ b/src/device/oprom/yabel/vbe.c
@@ -484,7 +484,7 @@ vbe_get_info(void)
DEBUG_PRINTF_VBE("DDC: edid_tranfer_time: %d\n",
ddc_info.edid_transfer_time);
DEBUG_PRINTF_VBE("DDC: ddc_level: %x\n", ddc_info.ddc_level);
- DEBUG_PRINTF_VBE("DDC: EDID: \n");
+ DEBUG_PRINTF_VBE("DDC: EDID:\n");
CHECK_DBG(DEBUG_VBE) {
dump(ddc_info.edid_block_zero,
sizeof(ddc_info.edid_block_zero));
diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c
index 9c51fff..87aa7f5 100644
--- a/src/drivers/i2c/w83795/w83795.c
+++ b/src/drivers/i2c/w83795/w83795.c
@@ -217,7 +217,7 @@ static void w83795_init(w83795_fan_mode_t mode, u8 dts_src)
/* Temperature ReadOut */
for (i = 0; i < 9; i++) {
val = w83795_read(W83795_REG_DTS(i));
- printk(BIOS_DEBUG, "DTS%x ReadOut=%x \n", i, val);
+ printk(BIOS_DEBUG, "DTS%x ReadOut=%x\n", i, val);
}
}
diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c
index f28e943..3b7dc6d 100644
--- a/src/drivers/intel/gma/intel_ddi.c
+++ b/src/drivers/intel/gma/intel_ddi.c
@@ -186,7 +186,7 @@ u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp,
temp |= TRANS_DDI_BPC_12;
break;
default:
- printk(BIOS_ERR, "Invalid pipe_bpp: %d, *** Initialization will not succeed *** \n", pipe_bpp);
+ printk(BIOS_ERR, "Invalid pipe_bpp: %d, *** Initialization will not succeed ***\n", pipe_bpp);
}
if (port == PORT_A) {
diff --git a/src/drivers/intel/gma/intel_dp.c b/src/drivers/intel/gma/intel_dp.c
index 30c2568..44a947e 100644
--- a/src/drivers/intel/gma/intel_dp.c
+++ b/src/drivers/intel/gma/intel_dp.c
@@ -1687,7 +1687,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
/* Try 5 times, then try clock recovery if that fails */
if (tries > 5) {
- printk(BIOS_SPEW, "%s: tries > 5,recovering. \n",
+ printk(BIOS_SPEW, "%s: tries > 5,recovering.\n",
__func__);
intel_dp_link_down(intel_dp);
intel_dp_start_link_train(intel_dp);
diff --git a/src/lib/libgcov.c b/src/lib/libgcov.c
index dbbd709..11776a1 100644
--- a/src/lib/libgcov.c
+++ b/src/lib/libgcov.c
@@ -253,7 +253,7 @@ buffer_fn_data (const char *filename, const struct gcov_info *gi_ptr,
return &fn_buffer->next;
fail:
- fprintf (stderr, "profiling:%s:Function %u %s %u \n", filename, fn_ix,
+ fprintf (stderr, "profiling:%s:Function %u %s %u\n", filename, fn_ix,
len ? "cannot allocate" : "counter mismatch", len ? len : ix);
return (struct gcov_fn_buffer **)free_fn_data (gi_ptr, fn_buffer, ix);
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index 2402798..20cb703 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -115,10 +115,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -163,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
post_code(0x39);
if (!warm_reset_detect(0)) { // BSP is node 0
@@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
rs780_htinit();
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 5c5b44f..e6646f5 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -107,10 +107,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
@@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
rs780_htinit();
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index 1156ec4..842b4f0 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -76,8 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
if(boot_cpu()) {
post_code(0x34);
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 489e81f..468f896 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -71,8 +71,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35);
AGESAWRAPPER(amdinitmmio);
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 278a3bd..13470e2 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -109,10 +109,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
@@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
rs780_htinit();
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 718a057..326a41a 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -68,8 +68,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
int i;
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 7bd3984..7c143f4 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -59,8 +59,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index b0fd12c..5d530b7 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -76,8 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35);
AGESAWRAPPER(amdinitmmio);
diff --git a/src/mainboard/amd/serengeti_cheetah/irq_tables.c b/src/mainboard/amd/serengeti_cheetah/irq_tables.c
index 0dd0dac..4d42f47 100644
--- a/src/mainboard/amd/serengeti_cheetah/irq_tables.c
+++ b/src/mainboard/amd/serengeti_cheetah/irq_tables.c
@@ -98,13 +98,13 @@ unsigned long write_pirq_routing_table(unsigned long addr)
}
//pci bridge
- printk(BIOS_DEBUG, "setting Onboard AMD Southbridge \n");
+ printk(BIOS_DEBUG, "setting Onboard AMD Southbridge\n");
static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 };
pci_assign_irqs(m->bus_8111_0, sysconf.sbdn+1, slotIrqs_1_4);
write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
- printk(BIOS_DEBUG, "setting Onboard AMD USB \n");
+ printk(BIOS_DEBUG, "setting Onboard AMD USB\n");
static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11};
pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0);
write_pirq_info(pirq_info, m->bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0);
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 09b86bb..6388b42 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -64,7 +64,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl)
int ret,i;
u8 device = ctrl->spd_switch_addr;
- printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x \n", device, ctrl->node_id);
+ printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x\n", device, ctrl->node_id);
/* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
i=2;
@@ -215,10 +215,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -260,7 +260,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
@@ -278,7 +278,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index a66c2b8..98a042a 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -71,8 +71,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35);
AGESAWRAPPER(amdinitmmio);
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index f3108ff..8ee42bd 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -76,8 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 6e28cbd..f5ac2e0 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -109,10 +109,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
@@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
rs780_htinit();
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index febe120..7ed520a 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -68,8 +68,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x36);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 531d3b4..168b57f 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -65,8 +65,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35);
AGESAWRAPPER(amdinitmmio);
diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c
index dc5fd45..6ee2704 100644
--- a/src/mainboard/arima/hdama/mptable.c
+++ b/src/mainboard/arima/hdama/mptable.c
@@ -217,7 +217,7 @@ static void reboot_if_hotswap(void)
printk(BIOS_DEBUG, "Looking for bad PCIX MHz input\n");
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
if (!dev)
- printk(BIOS_DEBUG, "Couldn't find %02x:02.0 \n", bus_chain_0);
+ printk(BIOS_DEBUG, "Couldn't find %02x:02.0\n", bus_chain_0);
else {
data = pci_read_config32(dev, 0xa0);
if(!(((data>>16)&0x03)==0x03)) {
@@ -228,7 +228,7 @@ static void reboot_if_hotswap(void)
printk(BIOS_DEBUG, "Looking for bad Hot Swap Enable\n");
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
if (!dev)
- printk(BIOS_DEBUG, "Couldn't find %02x:01.0 \n", bus_chain_0);
+ printk(BIOS_DEBUG, "Couldn't find %02x:01.0\n", bus_chain_0);
else {
data = pci_read_config32(dev, 0x48);
if(data & 0x0c) {
diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
index 073d2b8..7276b30 100644
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ b/src/mainboard/artecgroup/dbe61/romstage.c
@@ -101,7 +101,7 @@ void main(unsigned long bist)
print_debug_hex32(msr.hi);
print_debug(":");
print_debug_hex32(msr.lo);
- print_debug(" \n");
+ print_debug("\n");
msr = rdmsr(MC_CF1017_DATA);
print_debug("MC_CF1017_DATA: ");
@@ -110,7 +110,7 @@ void main(unsigned long bist)
print_debug_hex32(msr.hi);
print_debug(":");
print_debug_hex32(msr.lo);
- print_debug(" \n");
+ print_debug("\n");
msr = rdmsr(MC_CF8F_DATA);
print_debug("MC_CF8F_DATA: ");
@@ -120,6 +120,6 @@ void main(unsigned long bist)
print_debug(":");
print_debug_hex32(msr.lo);
msr = rdmsr(MC_CF8F_DATA);
- print_debug(" \n");
+ print_debug("\n");
#endif
}
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index a0a2912..5223360 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -71,8 +71,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35);
AGESAWRAPPER(amdinitmmio);
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index b750e44..37f14f6 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -92,8 +92,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
int i;
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index 1dea57b..c137b14 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -64,7 +64,7 @@ void soft_reset(void)
uint8_t tmp;
set_bios_reset();
- print_debug("soft reset \n");
+ print_debug("soft reset\n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index abe5f84..5c78ab1 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -64,7 +64,7 @@ void soft_reset(void)
uint8_t tmp;
set_bios_reset();
- print_debug("soft reset \n");
+ print_debug("soft reset\n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index 71455fd..bdf03a7 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -124,8 +124,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index 4d6bd60..15b8682 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -62,7 +62,7 @@ void soft_reset(void)
uint8_t tmp;
set_bios_reset();
- print_debug("soft reset \n");
+ print_debug("soft reset\n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index d374828..adcdfc7 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -91,7 +91,7 @@ void soft_reset(void)
uint8_t tmp;
set_bios_reset();
- print_debug("soft reset \n");
+ print_debug("soft reset\n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -134,7 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
enable_rom_decode();
- printk(BIOS_INFO, "now booting... \n");
+ printk(BIOS_INFO, "now booting...\n");
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index a2c6a03..30ba468 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -234,7 +234,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
m2v_it8712f_gpio_init();
ite_enable_3vsbsw(GPIO_DEV);
- printk(BIOS_INFO, "now booting... \n");
+ printk(BIOS_INFO, "now booting...\n");
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 2620a13..0a03d59 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -111,10 +111,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -160,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
@@ -178,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
rs780_htinit();
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index ff04dc7..84d2b97 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -111,10 +111,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -160,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
@@ -178,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
rs780_htinit();
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 9fca93f..4753bb0 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -112,10 +112,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -160,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
post_code(0x39);
if (!warm_reset_detect(0)) { // BSP is node 0
@@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
rs780_htinit();
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 883bd11..65f499b 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -116,10 +116,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -164,7 +164,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
post_code(0x39);
if (!warm_reset_detect(0)) { // BSP is node 0
@@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
rs780_htinit();
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 62a9211..a0f9e76 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -106,10 +106,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
@@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
rs780_htinit();
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 62a9211..a0f9e76 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -106,10 +106,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
@@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
rs780_htinit();
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index a437009..b9d27f7 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -109,10 +109,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
@@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
rs780_htinit();
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 420efc3..b4af6d4 100755
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -84,8 +84,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35);
AGESAWRAPPER(amdinitmmio);
diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c
index bbd8405..6c71bad 100644
--- a/src/mainboard/hp/dl145_g3/mptable.c
+++ b/src/mainboard/hp/dl145_g3/mptable.c
@@ -124,7 +124,7 @@ static void *smp_write_config_table(void *v)
printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
//USB
- printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x \n",sysconf.sbdn, m->bus_bcm5785_0);
+ printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x\n",sysconf.sbdn, m->bus_bcm5785_0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03<<2)|0, m->apicid_bcm5785[0], 0xa);
//VGA
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
index 7855cd1..ea848b4 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
@@ -56,8 +56,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 612ff1a..e1230e5 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -109,10 +109,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
@@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
rs780_htinit();
diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c
index 39fce07..4da6fe7 100644
--- a/src/mainboard/iwave/iWRainbowG6/romstage.c
+++ b/src/mainboard/iwave/iWRainbowG6/romstage.c
@@ -291,7 +291,7 @@ static void sch_shadow_CMC(void)
/* FIXME: proper dest, proper src, and wbinvd, too */
memcpy((void *)CMC_SHADOW, (void *)0xfffd0000, 64 * 1024);
- // __asm__ volatile ("wbinvd \n"
+ // __asm__ volatile ("wbinvd\n"
//);
printk(BIOS_DEBUG, "copy done ");
memcpy((void *)0x3f5f0000, (void *)0x3faf0000, 64 * 1024);
diff --git a/src/mainboard/iwill/dk8_htx/irq_tables.c b/src/mainboard/iwill/dk8_htx/irq_tables.c
index 0dd0dac..4d42f47 100644
--- a/src/mainboard/iwill/dk8_htx/irq_tables.c
+++ b/src/mainboard/iwill/dk8_htx/irq_tables.c
@@ -98,13 +98,13 @@ unsigned long write_pirq_routing_table(unsigned long addr)
}
//pci bridge
- printk(BIOS_DEBUG, "setting Onboard AMD Southbridge \n");
+ printk(BIOS_DEBUG, "setting Onboard AMD Southbridge\n");
static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 };
pci_assign_irqs(m->bus_8111_0, sysconf.sbdn+1, slotIrqs_1_4);
write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
- printk(BIOS_DEBUG, "setting Onboard AMD USB \n");
+ printk(BIOS_DEBUG, "setting Onboard AMD USB\n");
static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11};
pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0);
write_pirq_info(pirq_info, m->bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0);
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 4b2f711..7f91714 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -92,8 +92,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35);
AGESAWRAPPER(amdinitmmio);
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 044d0d8..5121605 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -114,10 +114,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -163,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
@@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
rs780_htinit();
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index 05c5019..61fd6bd 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -75,8 +75,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35);
AGESAWRAPPER(amdinitmmio);
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 595faa0..f9b9adf 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -76,8 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35);
AGESAWRAPPER(amdinitmmio);
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index cd185f3..b393c34 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -130,10 +130,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n", sysinfo, sysinfo + 1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n",
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n",
msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
@@ -195,7 +195,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n",
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n",
msr.hi, msr.lo);
#endif
diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c
index 8ee89a7..294410c 100644
--- a/src/mainboard/supermicro/h8qgi/agesawrapper.c
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c
@@ -1000,7 +1000,7 @@ static void agesa_critical(EVENT_PARAMS *event)
break;
case HT_EVENT_COH_PROCESSOR_TYPE_MIX:
- printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n",
+ printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX\n",
(unsigned int)event->DataParam1,
(unsigned int)event->DataParam2,
(unsigned int)event->DataParam3);
@@ -1184,6 +1184,6 @@ AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus)
Status = AmdReadEventLog(&AmdEventParams);
}
- printk(BIOS_DEBUG, "exit %s \n", __func__);
+ printk(BIOS_DEBUG, "exit %s\n", __func__);
return Status;
}
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index 4273fdb..425f677 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -62,8 +62,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 9898a25..24ecb5d 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -197,10 +197,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -242,7 +242,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
* need to be done once.*/
@@ -260,7 +260,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
init_timer(); // Need to use TMICT to synconize FID/VID
diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.c b/src/mainboard/supermicro/h8scm/agesawrapper.c
index c52197b..b3c0bd2 100644
--- a/src/mainboard/supermicro/h8scm/agesawrapper.c
+++ b/src/mainboard/supermicro/h8scm/agesawrapper.c
@@ -1000,7 +1000,7 @@ static void agesa_critical(EVENT_PARAMS *event)
break;
case HT_EVENT_COH_PROCESSOR_TYPE_MIX:
- printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n",
+ printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX\n",
(unsigned int)event->DataParam1,
(unsigned int)event->DataParam2,
(unsigned int)event->DataParam3);
@@ -1184,6 +1184,6 @@ AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus)
Status = AmdReadEventLog(&AmdEventParams);
}
- printk(BIOS_DEBUG, "exit %s \n", __func__);
+ printk(BIOS_DEBUG, "exit %s\n", __func__);
return Status;
}
diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c
index 4084add..da92d97 100644
--- a/src/mainboard/supermicro/h8scm/romstage.c
+++ b/src/mainboard/supermicro/h8scm/romstage.c
@@ -61,8 +61,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 216e5df..fdf49d8 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -120,10 +120,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -171,7 +171,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
@@ -189,7 +189,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
sr5650_htinit();
diff --git a/src/mainboard/tyan/s2882/irq_tables.c b/src/mainboard/tyan/s2882/irq_tables.c
index 20c10da..218ddce 100644
--- a/src/mainboard/tyan/s2882/irq_tables.c
+++ b/src/mainboard/tyan/s2882/irq_tables.c
@@ -197,13 +197,13 @@ unsigned long write_pirq_routing_table(unsigned long addr)
}
}
- printk(BIOS_DEBUG, "setting Onboard AMD Southbridge \n");
+ printk(BIOS_DEBUG, "setting Onboard AMD Southbridge\n");
static const unsigned char slotIrqs_1_4[4] = { 5, 9, 11, 10 };
pci_assign_irqs(bus_chain_0, 4, slotIrqs_1_4);
write_pirq_info(pirq_info, bus_chain_0,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
- printk(BIOS_DEBUG, "setting Onboard AMD USB \n");
+ printk(BIOS_DEBUG, "setting Onboard AMD USB\n");
static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 10 };
pci_assign_irqs(bus_8111_1, 0, slotIrqs_8111_1_0);
write_pirq_info(pirq_info, bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0);
@@ -239,7 +239,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
write_pirq_info(pirq_info, bus_8131_1,(2<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x4, 0);
pirq_info++; slot_num++;
- printk(BIOS_DEBUG, "setting Slot 5 \n");
+ printk(BIOS_DEBUG, "setting Slot 5\n");
static const unsigned char slotIrqs_8111_1_4[4] = { 5, 9, 11, 10 };
pci_assign_irqs(bus_8111_1, 4, slotIrqs_8111_1_4);
write_pirq_info(pirq_info, bus_8111_1,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x5, 0);
diff --git a/src/mainboard/tyan/s8226/agesawrapper.c b/src/mainboard/tyan/s8226/agesawrapper.c
index 425054c..9f66b4c 100644
--- a/src/mainboard/tyan/s8226/agesawrapper.c
+++ b/src/mainboard/tyan/s8226/agesawrapper.c
@@ -1007,7 +1007,7 @@ static void agesa_critical(EVENT_PARAMS *event)
break;
case HT_EVENT_COH_PROCESSOR_TYPE_MIX:
- printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n",
+ printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX\n",
(unsigned int)event->DataParam1,
(unsigned int)event->DataParam2,
(unsigned int)event->DataParam3);
@@ -1191,6 +1191,6 @@ AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus)
Status = AmdReadEventLog(&AmdEventParams);
}
- printk(BIOS_DEBUG, "exit %s \n", __func__);
+ printk(BIOS_DEBUG, "exit %s\n", __func__);
return Status;
}
diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c
index 9624af8..dc3bde2 100644
--- a/src/mainboard/tyan/s8226/romstage.c
+++ b/src/mainboard/tyan/s8226/romstage.c
@@ -61,8 +61,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index e01fd4b..6198cda 100644
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -117,7 +117,7 @@ static void enable_mainboard_devices(void)
pci_write_config8(dev, 0x5b, 0x01);
#endif
- print_debug("In enable_mainboard_devices \n");
+ print_debug("In enable_mainboard_devices\n");
/* Enable P2P Bridge Header for external PCI bus. */
dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0);
@@ -634,7 +634,7 @@ void main(unsigned long bist)
);
#endif
/* This can have function call, because no variable used before this. */
- print_debug("Copy memory to high memory to protect s3 wakeup vector code \n");
+ print_debug("Copy memory to high memory to protect s3 wakeup vector code\n");
memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 -
0x100000), (unsigned char *)0, 0xa0000);
memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 -
diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c
index 9368028..ece64d8 100644
--- a/src/mainboard/via/epia-m850/romstage.c
+++ b/src/mainboard/via/epia-m850/romstage.c
@@ -55,7 +55,7 @@ void main(unsigned long bist)
/* Serial console is easy to take care of */
fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
- print_debug("Console initialized. \n");
+ print_debug("Console initialized.\n");
vx900_cpu_bus_interface_setup();
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index e5c18a8..d846682 100644
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -219,7 +219,7 @@ u32 mctGetLogicalCPUID(u32 Node)
break;
default:
/* FIXME: mabe we should die() here. */
- print_err("FIXME! CPU Version unknown or not supported! \n");
+ print_err("FIXME! CPU Version unknown or not supported!\n");
ret = 0;
}
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 66eb88a..32ba809 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -636,7 +636,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
devx = pDCTstat->dev_map;
if (pDCTstat->NodePresent) {
- printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x \n", Node);
+ printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x\n", Node);
reg = 0x40; /*Dram Base 0*/
do {
val = Get_NB32(dev, reg);
@@ -879,7 +879,7 @@ static void StartupDCT_D(struct MCTStatStruc *pMCTstat,
byte = mctGet_NVbits(NV_DQSTrainCTL);
if (byte == 1) {
/* Enable DQSRcvEn training mode */
- print_t("\t\t\tStartupDCT_D: DqsRcvEnTrain set \n");
+ print_t("\t\t\tStartupDCT_D: DqsRcvEnTrain set\n");
reg = 0x78 + reg_off;
val = Get_NB32(dev, reg);
/* Setting this bit forces a 1T window with hard left
@@ -890,7 +890,7 @@ static void StartupDCT_D(struct MCTStatStruc *pMCTstat,
Set_NB32(dev, reg, val);
}
mctHookBeforeDramInit(); /* generalized Hook */
- print_t("\t\t\tStartupDCT_D: DramInit \n");
+ print_t("\t\t\tStartupDCT_D: DramInit\n");
mct_DramInit(pMCTstat, pDCTstat, dct);
AfterDramInit_D(pDCTstat, dct);
mctHookAfterDramInit(); /* generalized Hook*/
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 90b7ed3..eb45ef8 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -630,7 +630,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
val |= Node;
Set_NB32(dev, 0x44 + (Node << 3), val); /* set DstNode */
- printk(BIOS_DEBUG, " Node: %02x base: %02x limit: %02x \n", Node, base, limit);
+ printk(BIOS_DEBUG, " Node: %02x base: %02x limit: %02x\n", Node, base, limit);
limit = pDCTstat->DCTSysLimit;
if (limit) {
NextBase = (limit & 0xFFFF0000) + 0x10000;
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index e127322..15552d5 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -394,7 +394,7 @@ static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTs
print_t("vErrata350: Address not supported on current CS\n");
continue;
}
- print_t("vErrata350: dummy read \n");
+ print_t("vErrata350: dummy read\n");
read32_fs(u32Addr);
}
}
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 02cafe9..5e6d1a5 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -1251,7 +1251,7 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo)
u32 chan0dll = 0, chan1dll = 0;
int i;
- printk(BIOS_DEBUG, "Programming DLL Timings... \n");
+ printk(BIOS_DEBUG, "Programming DLL Timings...\n");
MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
@@ -1303,7 +1303,7 @@ static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
u8 reg8;
u32 reg32;
- printk(BIOS_DEBUG, "Initializing System Memory IO... \n");
+ printk(BIOS_DEBUG, "Initializing System Memory IO...\n");
/* Enable Data Half Clock Pushout */
reg8 = MCHBAR8(C0HCTC);
reg8 &= ~0x1f;
@@ -1345,7 +1345,7 @@ static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
{
u32 reg32;
- printk(BIOS_DEBUG, "Enabling System Memory IO... \n");
+ printk(BIOS_DEBUG, "Enabling System Memory IO...\n");
reg32 = MCHBAR32(RCVENMT);
reg32 &= ~(0x3f << 6);
@@ -1521,7 +1521,7 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
int i;
int cum0, cum1, tolud, tom;
- printk(BIOS_DEBUG, "Setting RAM size... \n");
+ printk(BIOS_DEBUG, "Setting RAM size...\n");
cum0 = 0;
for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
@@ -1577,7 +1577,7 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo)
int i, value;
u16 dra0=0, dra1=0, dra = 0;
- printk(BIOS_DEBUG, "Setting row attributes... \n");
+ printk(BIOS_DEBUG, "Setting row attributes...\n");
for(i=0; i < 2 * DIMM_SOCKETS; i++) {
u16 device;
u8 columnsrows;
@@ -2779,7 +2779,7 @@ static void sdram_on_die_termination(struct sys_info *sysinfo)
if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
- printk(BIOS_DEBUG, "one dimm per channel config.. \n");
+ printk(BIOS_DEBUG, "one dimm per channel config..\n");
reg32 = MCHBAR32(C0ODT);
reg32 &= ~(7 << 28);
diff --git a/src/northbridge/intel/sch/raminit.c b/src/northbridge/intel/sch/raminit.c
index 8689c6f..41956e3 100644
--- a/src/northbridge/intel/sch/raminit.c
+++ b/src/northbridge/intel/sch/raminit.c
@@ -216,7 +216,7 @@ static void do_jedec_init(struct sys_info *sysinfo)
if (rank == 0)
program_dll_config(sysinfo);
- printk(BIOS_DEBUG, "Setting up RAM \n");
+ printk(BIOS_DEBUG, "Setting up RAM\n");
/*
* Wait 200us
diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c
index 3f9c70f..6a15f9a 100644
--- a/src/northbridge/via/vx800/examples/chipset_init.c
+++ b/src/northbridge/via/vx800/examples/chipset_init.c
@@ -639,7 +639,7 @@ void main(void)
//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x00, 0x76);//open all usb and usb mode
//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x76, 0x76);//close all usb
- printk(BIOS_INFO, "=================SB 50h=%02x \n",
+ printk(BIOS_INFO, "=================SB 50h=%02x\n",
pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x50));
/* FIXME: Is there a better way to handle this? */
@@ -651,7 +651,7 @@ void main(void)
printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
#if 0
x = y = 0;
- printk(BIOS_INFO, "dump ehci3 \n");
+ printk(BIOS_INFO, "dump ehci3\n");
for (; x < 16; x++) {
y = 0;
for (; y < 16; y++) {
@@ -670,7 +670,7 @@ void main(void)
printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
#if 0
x = y = 0;
- printk(BIOS_INFO, "dump ehci3 \n");
+ printk(BIOS_INFO, "dump ehci3\n");
for (; x < 16; x++) {
y = 0;
for (; y < 16; y++) {
@@ -688,7 +688,7 @@ void main(void)
/* And of course initialize devices on the bus */
#if 0
x = y = 0;
- printk(BIOS_INFO, "dump ehci3 \n");
+ printk(BIOS_INFO, "dump ehci3\n");
for (; x < 16; x++) {
y = 0;
for (; y < 16; y++) {
@@ -707,7 +707,7 @@ void main(void)
#if 0
x = y = 0;
- printk(BIOS_INFO, "dump ehci3 \n");
+ printk(BIOS_INFO, "dump ehci3\n");
for (; x < 16; x++) {
y = 0;
for (; y < 16; y++) {
diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index 2ab3e64..e18adf4 100644
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -75,7 +75,7 @@ static void enable_mainboard_devices(void)
device_t dev;
uint16_t values;
- print_debug("In enable_mainboard_devices \n");
+ print_debug("In enable_mainboard_devices\n");
/* Enable P2P bridge Header for external PCI bus. */
dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0);
@@ -511,7 +511,7 @@ g) Rx73h = 32h
"rep movsd\n\t"
::"g"(memtop4)
);*/
- print_debug("copy memory to high memory to protect s3 wakeup vector code \n"); //this can have function call, because no variable used before this
+ print_debug("copy memory to high memory to protect s3 wakeup vector code\n"); //this can have function call, because no variable used before this
memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) -
64 * 1024 - 0x100000),
(unsigned char *) 0, 0xa0000);
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
index 53cada3..0666f98 100644
--- a/src/northbridge/via/vx900/northbridge.c
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -85,8 +85,8 @@ static void killme_debug_4g_remap_reg(u32 reg32)
u64 remapend = (reg32 >> 14) & 0x3ff;
remapstart <<= 26;
remapend <<= 26;
- printk(BIOS_DEBUG, "Remapstart %lld(MB) \n", remapstart >> 20);
- printk(BIOS_DEBUG, "Remapend %lld(MB) \n", remapend >> 20);
+ printk(BIOS_DEBUG, "Remapstart %lld(MB)\n", remapstart >> 20);
+ printk(BIOS_DEBUG, "Remapend %lld(MB)\n", remapend >> 20);
}
/**
diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c
index 88e421e..568471d 100644
--- a/src/southbridge/amd/amd8132/bridge.c
+++ b/src/southbridge/amd/amd8132/bridge.c
@@ -156,7 +156,7 @@ static unsigned int amd8132_scan_bus(struct bus *bus,
info.sstatus = pci_read_config16(bus->dev, pos + PCI_X_SEC_STATUS);
/* Print the PCI-X bus speed */
- printk(BIOS_DEBUG, "PCI: %02x: %s sstatus=%04x rev=%02x \n", bus->secondary, pcix_speed(info.sstatus), info.sstatus, info.rev);
+ printk(BIOS_DEBUG, "PCI: %02x: %s sstatus=%04x rev=%02x\n", bus->secondary, pcix_speed(info.sstatus), info.sstatus, info.rev);
/* Examine the bus and find out how loaded it is */
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index 2825925..fdea775 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -201,7 +201,7 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
{
tempdev = dev_find_slot(Bus, Dev << 3);
Value = pci_read_config32(tempdev, 0);
- printk(BIOS_DEBUG, "Dev ID %x \n", Value);
+ printk(BIOS_DEBUG, "Dev ID %x\n", Value);
if((Value & 0xffff) == 0x1102)
{//Creative
//Found Creative SB
@@ -232,7 +232,7 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
}
}
}
- printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit);
+ printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x\n", MMIOStart, MMIOLimit);
if (MMIOStart < MMIOLimit)
{
Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO);
@@ -574,44 +574,44 @@ static void internal_gfx_pci_dev_init(struct device *dev)
poweron_ddi_lanes(nb_dev);
printk(BIOS_DEBUG,"vgainfo:\n"
- " ulBootUpEngineClock:%lu \n"
- " ulBootUpUMAClock:%lu \n"
- " ulBootUpSidePortClock:%lu \n"
- " ulMinSidePortClock:%lu \n"
- " ulSystemConfig:%lu \n"
- " ulBootUpReqDisplayVector:%lu \n"
- " ulOtherDisplayMisc:%lu \n"
- " ulDDISlot1Config:%lu \n"
- " ulDDISlot2Config:%lu \n"
-
- " ucMemoryType:%u \n"
- " ucUMAChannelNumber:%u \n"
- " ucDockingPinBit:%u \n"
- " ucDockingPinPolarity:%u \n"
-
- " ulDockingPinCFGInfo:%lu \n"
- " ulCPUCapInfo: %lu \n"
-
- " usNumberOfCyclesInPeriod:%hu \n"
- " usMaxNBVoltage:%hu \n"
- " usMinNBVoltage:%hu \n"
- " usBootUpNBVoltage:%hu \n"
-
- " ulHTLinkFreq:%lu \n"
-
- " usMinHTLinkWidth:%hu \n"
- " usMaxHTLinkWidth:%hu \n"
- " usUMASyncStartDelay:%hu \n"
- " usUMADataReturnTime:%hu \n"
- " usLinkStatusZeroTime:%hu \n"
-
- " ulHighVoltageHTLinkFreq:%lu \n"
- " ulLowVoltageHTLinkFreq:%lu \n"
-
- " usMaxUpStreamHTLinkWidth:%hu \n"
- " usMaxDownStreamHTLinkWidth:%hu \n"
- " usMinUpStreamHTLinkWidth:%hu \n"
- " usMinDownStreamHTLinkWidth:%hu \n",
+ " ulBootUpEngineClock:%lu\n"
+ " ulBootUpUMAClock:%lu\n"
+ " ulBootUpSidePortClock:%lu\n"
+ " ulMinSidePortClock:%lu\n"
+ " ulSystemConfig:%lu\n"
+ " ulBootUpReqDisplayVector:%lu\n"
+ " ulOtherDisplayMisc:%lu\n"
+ " ulDDISlot1Config:%lu\n"
+ " ulDDISlot2Config:%lu\n"
+
+ " ucMemoryType:%u\n"
+ " ucUMAChannelNumber:%u\n"
+ " ucDockingPinBit:%u\n"
+ " ucDockingPinPolarity:%u\n"
+
+ " ulDockingPinCFGInfo:%lu\n"
+ " ulCPUCapInfo: %lu\n"
+
+ " usNumberOfCyclesInPeriod:%hu\n"
+ " usMaxNBVoltage:%hu\n"
+ " usMinNBVoltage:%hu\n"
+ " usBootUpNBVoltage:%hu\n"
+
+ " ulHTLinkFreq:%lu\n"
+
+ " usMinHTLinkWidth:%hu\n"
+ " usMaxHTLinkWidth:%hu\n"
+ " usUMASyncStartDelay:%hu\n"
+ " usUMADataReturnTime:%hu\n"
+ " usLinkStatusZeroTime:%hu\n"
+
+ " ulHighVoltageHTLinkFreq:%lu\n"
+ " ulLowVoltageHTLinkFreq:%lu\n"
+
+ " usMaxUpStreamHTLinkWidth:%hu\n"
+ " usMaxDownStreamHTLinkWidth:%hu\n"
+ " usMinUpStreamHTLinkWidth:%hu\n"
+ " usMinDownStreamHTLinkWidth:%hu\n",
(unsigned long)vgainfo.ulBootUpEngineClock,
(unsigned long)vgainfo.ulBootUpUMAClock,
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index b3a9b00..a4d59c0 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -111,7 +111,7 @@ static void lpc_init(device_t dev)
lpc_common_init(dev);
pm_base = pci_read_config32(dev, 0x60) & 0xff00;
- printk(BIOS_INFO, "%s: pm_base = %x \n", __func__, pm_base);
+ printk(BIOS_INFO, "%s: pm_base = %x\n", __func__, pm_base);
#if CK804_CHIP_REV == 1
if (dev->bus->secondary != 1)
diff --git a/src/southbridge/nvidia/ck804/sata.c b/src/southbridge/nvidia/ck804/sata.c
index bcf4200..e8e4fb1 100644
--- a/src/southbridge/nvidia/ck804/sata.c
+++ b/src/southbridge/nvidia/ck804/sata.c
@@ -111,7 +111,7 @@ static void sata_init(struct device *dev)
if (conf->sata0_enable) {
/* Enable primary SATA interface. */
dword |= (1 << 1);
- printk(BIOS_DEBUG, "SATA P \n");
+ printk(BIOS_DEBUG, "SATA P\n");
}
#if 0
/* Write back */
diff --git a/src/southbridge/nvidia/mcp55/sata.c b/src/southbridge/nvidia/mcp55/sata.c
index 0501548..58bc807 100644
--- a/src/southbridge/nvidia/mcp55/sata.c
+++ b/src/southbridge/nvidia/mcp55/sata.c
@@ -48,11 +48,11 @@ static void sata_init(struct device *dev)
if (conf->sata0_enable) {
/* Enable primary SATA interface */
dword |= (1<<1);
- printk(BIOS_DEBUG, "SATA P \n");
+ printk(BIOS_DEBUG, "SATA P\n");
}
} else {
dword |= (1<<1) | (1<<0);
- printk(BIOS_DEBUG, "SATA P and S \n");
+ printk(BIOS_DEBUG, "SATA P and S\n");
}
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c
index 0efcafa..ab13957 100644
--- a/src/southbridge/ricoh/rl5c476/rl5c476.c
+++ b/src/southbridge/ricoh/rl5c476/rl5c476.c
@@ -184,7 +184,7 @@ static void rl5c476_read_resources(device_t dev)
static void rl5c476_set_resources(device_t dev)
{
struct resource *resource;
- printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev));
+ printk(BIOS_DEBUG, "%s In set resources\n",dev_path(dev));
if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
resource = find_resource(dev,1);
if( !(resource->flags & IORESOURCE_STORED) ){
diff --git a/src/southbridge/sis/sis966/aza.c b/src/southbridge/sis/sis966/aza.c
index 7e148cf..f3a9055 100644
--- a/src/southbridge/sis/sis966/aza.c
+++ b/src/southbridge/sis/sis966/aza.c
@@ -104,7 +104,7 @@ static int codec_detect(u32 base)
do{
dword = read32(base + 0x08)&0x1;
- if(idx++>1000) { printk(BIOS_DEBUG, "controller reset fail !!! \n"); break;}
+ if(idx++>1000) { printk(BIOS_DEBUG, "controller reset fail !!!\n"); break;}
} while (dword !=1);
dword=send_verb(base,0x000F0000); // get codec VendorId and DeviceId
diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c
index 18ed75e..d52e851 100644
--- a/src/southbridge/sis/sis966/nic.c
+++ b/src/southbridge/sis/sis966/nic.c
@@ -225,7 +225,7 @@ static int phy_detect(u32 base,u16 *PhyAddr) //BOOL PHY_Detect()
if(!bFoundPhy)
{
- printk(BIOS_DEBUG, "PHY not found !!!! \n");
+ printk(BIOS_DEBUG, "PHY not found !!!!\n");
}
*PhyAddr=PhyAddress;
@@ -287,7 +287,7 @@ static void nic_init(struct device *dev)
// if that is valid we will use that
- printk(BIOS_DEBUG, "EEPROM contents %lx \n",ReadEEprom( dev, base, 0LL));
+ printk(BIOS_DEBUG, "EEPROM contents %lx\n",ReadEEprom( dev, base, 0LL));
for(i=0;i<3;i++) {
//status = smbus_read_byte(dev_eeprom, i);
ulValue=ReadEEprom( dev, base, i+3L);
@@ -298,7 +298,7 @@ static void nic_init(struct device *dev)
}
}else{
// read MAC address from firmware
- printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue);
+ printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx\n",ulValue);
MacAddr[0]=read16(0xffffffc0); // mac address store at here
MacAddr[1]=read16(0xffffffc2);
MacAddr[2]=read16(0xffffffc4);
diff --git a/src/southbridge/ti/pci7420/cardbus.c b/src/southbridge/ti/pci7420/cardbus.c
index 2ab383b..64878b3 100644
--- a/src/southbridge/ti/pci7420/cardbus.c
+++ b/src/southbridge/ti/pci7420/cardbus.c
@@ -90,11 +90,11 @@ static void pci7420_cardbus_read_resources(device_t dev)
static void pci7420_cardbus_set_resources(device_t dev)
{
- printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev));
+ printk(BIOS_DEBUG, "%s In set resources\n",dev_path(dev));
pci_dev_set_resources(dev);
- printk(BIOS_DEBUG, "%s done set resources \n",dev_path(dev));
+ printk(BIOS_DEBUG, "%s done set resources\n",dev_path(dev));
}
static struct device_operations ti_pci7420_ops = {
diff --git a/src/southbridge/ti/pcixx12/pcixx12.c b/src/southbridge/ti/pcixx12/pcixx12.c
index 5e62292..abddba1 100644
--- a/src/southbridge/ti/pcixx12/pcixx12.c
+++ b/src/southbridge/ti/pcixx12/pcixx12.c
@@ -38,11 +38,11 @@ static void pcixx12_read_resources(device_t dev)
static void pcixx12_set_resources(device_t dev)
{
- printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev));
+ printk(BIOS_DEBUG, "%s In set resources\n",dev_path(dev));
pci_dev_set_resources(dev);
- printk(BIOS_DEBUG, "%s done set resources \n",dev_path(dev));
+ printk(BIOS_DEBUG, "%s done set resources\n",dev_path(dev));
}
static struct device_operations ti_pcixx12_ops = {
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f10/Proc/Common/S3RestoreState.c
index 3d98b38..5e5e235 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/S3RestoreState.c
@@ -298,7 +298,7 @@ S3RestoreStateFromTable (
return AGESA_ERROR;
}
}
- IDS_HDT_CONSOLE (" End S3 Restore \n");
+ IDS_HDT_CONSOLE (" End S3 Restore\n");
return AGESA_SUCCESS;
}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mprhy3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mprhy3.c
index a65220b..8ef8909 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mprhy3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mprhy3.c
@@ -288,7 +288,7 @@ MemPGetPORFreqLimitRHy3 (
}
if (MaxDimmPerCH == 4) {
- printk(BIOS_DEBUG, "MAX 4 Dimms per channel configuration \n");
+ printk(BIOS_DEBUG, "MAX 4 Dimms per channel configuration\n");
DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid;
PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr);
@@ -296,15 +296,15 @@ MemPGetPORFreqLimitRHy3 (
NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
return;
} else if (MaxDimmPerCH == 3) {
- printk(BIOS_DEBUG, "MAX 3 Dimms per channel configuration \n");
+ printk(BIOS_DEBUG, "MAX 3 Dimms per channel configuration\n");
FreqLimitPtr = HyRDdr3PSPorFreqLimit3D;
FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit3D);
} else if (MaxDimmPerCH == 2) {
- printk(BIOS_DEBUG, "MAX 2 Dimms per channel configuration \n");
+ printk(BIOS_DEBUG, "MAX 2 Dimms per channel configuration\n");
FreqLimitPtr = HyRDdr3PSPorFreqLimit2D;
FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit2D);
} else {
- printk(BIOS_DEBUG, "MAX 1 Dimms per channel configuration \n");
+ printk(BIOS_DEBUG, "MAX 1 Dimms per channel configuration\n");
FreqLimitPtr = HyRDdr3PSPorFreqLimit1D;
FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit1D);
}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.c
index 7d4f728..a4ebdf1 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.c
@@ -514,7 +514,7 @@ MemTTrainDQSEdgeDetect (
}
} /// End Chip Select Loop
TechPtr->ChipSel = TechPtr->ChipSel - CsIndex;
- IDS_HDT_CONSOLE ("\t\t\t\tResult : %c %c %c %c %c %c %c %c \n",
+ IDS_HDT_CONSOLE ("\t\t\t\tResult : %c %c %c %c %c %c %c %c\n",
(SweepData.ResultFound & ((UINT16) 1 << (7))) ? ' ':(CurrentResult & ((UINT16) 1 << (7))) ? 'P':'.',
(SweepData.ResultFound & ((UINT16) 1 << (6))) ? ' ':(CurrentResult & ((UINT16) 1 << (6))) ? 'P':'.',
(SweepData.ResultFound & ((UINT16) 1 << (5))) ? ' ':(CurrentResult & ((UINT16) 1 << (5))) ? 'P':'.',
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f12/Proc/Common/S3RestoreState.c
index 7b2056b..aaa7382 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/S3RestoreState.c
@@ -435,7 +435,7 @@ S3RestoreStateFromTable (
return AGESA_ERROR;
}
}
- IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore \n");
+ IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore\n");
return AGESA_SUCCESS;
}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f12/Proc/Common/S3SaveState.c
index e194626..447fe23 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/S3SaveState.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/S3SaveState.c
@@ -481,7 +481,7 @@ S3SaveStateSaveInfoOp (
SaveOffsetPtr->OpCode = OpCode;
SaveOffsetPtr->Length = InformationLength;
S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", Information);
+ IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s\n", Information);
);
LibAmdMemCopy (
(UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER),
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c
index 4fe936f..7035611 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c
@@ -69,7 +69,7 @@ FchInitEnv (
FCH_DATA_BLOCK *FchParams;
AGESA_STATUS Status;
- IDS_HDT_CONSOLE (FCH_TRACE, " FchInitEnv Enter... \n");
+ IDS_HDT_CONSOLE (FCH_TRACE, " FchInitEnv Enter...\n");
FchParams = FchInitEnvCreatePrivateData (EnvParams);
// Override internal data with IDS (Optional, internal build only)
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitLate.c
index 58e24f7..89709a7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitLate.c
@@ -67,7 +67,7 @@ FchInitLate (
FCH_DATA_BLOCK *FchParams;
AGESA_STATUS Status;
- IDS_HDT_CONSOLE (FCH_TRACE, " FchInitLate Enter... \n");
+ IDS_HDT_CONSOLE (FCH_TRACE, " FchInitLate Enter...\n");
FchParams = FchInitLoadDataBlock (&LateParams->FchInterface, &LateParams->StdHeader);
Status = FchTaskLauncher (&FchInitLateTaskTable[0], FchParams);
IDS_HDT_CONSOLE (FCH_TRACE, " FchInitLate Exit... Status = [0x%x]\n", Status);
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitMid.c
index a259bde..9d3346b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitMid.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitMid.c
@@ -65,7 +65,7 @@ FchInitMid (
FCH_DATA_BLOCK *FchParams;
AGESA_STATUS Status;
- IDS_HDT_CONSOLE (FCH_TRACE, " FchInitMid Enter... \n");
+ IDS_HDT_CONSOLE (FCH_TRACE, " FchInitMid Enter...\n");
FchParams = FchInitLoadDataBlock (&MidParams->FchInterface, &MidParams->StdHeader);
Status = FchTaskLauncher (&FchInitMidTaskTable[0], FchParams);
IDS_HDT_CONSOLE (FCH_TRACE, " FchInitMid Exit... Status = [0x%x]\n", Status);
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLib.c
index e88d51e..c93e56f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLib.c
@@ -190,7 +190,7 @@ FchSataDriveDetectionFpga (
StdHeader = LocalCfgPtr->StdHeader;
TRACE ((DMSG_FCH_TRACE, "FCH - Entering sata drive detection procedure\n\n"));
- TRACE ((DMSG_FCH_TRACE, "SATA BAR5 is %X \n", *pBar5));
+ TRACE ((DMSG_FCH_TRACE, "SATA BAR5 is %X\n", *pBar5));
for ( PortNum = 0; PortNum < 4; PortNum++ ) {
ReadMem (*Bar5 + FCH_SATA_BAR5_REG128 + PortNum * 0x80, AccWidthUint32, &SataBarFpgaInfo);
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
index 7ecb6fa..c554188 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
@@ -685,7 +685,7 @@ GfxIntegratedDebugDumpPpTable (
ATOM_PPLIB_STATE_V2 *StatesPtr;
NON_CLOCK_INFO_ARRAY *NonClockInfoArrayPtr;
CLOCK_INFO_ARRAY *ClockInfoArrayPtr;
- IDS_HDT_CONSOLE (GFX_MISC, " < --- Power Play Table ------ > \n");
+ IDS_HDT_CONSOLE (GFX_MISC, " < --- Power Play Table ------ >\n");
IDS_HDT_CONSOLE (GFX_MISC, " Table Revision = %d\n", PpTable->ucDataRevision
);
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
index 90e9ca5..d0dfa1b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
@@ -185,7 +185,7 @@ GnbIommuIvrsTableDump (
UINT8 *Block;
UINT8 *Entry;
Block = (UINT8 *) Ivrs + sizeof (IOMMU_IVRS_HEADER);
- IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table Start -----------> \n");
+ IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table Start ----------->\n");
IDS_HDT_CONSOLE (GNB_TRACE, " IVInfo = 0x%08x\n", ((IOMMU_IVRS_HEADER *) Ivrs)-> IvInfo);
while (Block < ((UINT8 *) Ivrs + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength)) {
if (*Block == IvrsIvhdBlock) {
@@ -234,9 +234,9 @@ GnbIommuIvrsTableDump (
Block = Block + ((IVRS_IVHD_ENTRY *) Block)->Length;
}
}
- IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table Raw Data --------> \n");
+ IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table Raw Data -------->\n");
GnbLibDebugDumpBuffer (Ivrs, ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength, 1, 16);
IDS_HDT_CONSOLE (GNB_TRACE, "\n");
- IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table End -------------> \n");
+ IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table End ------------->\n");
}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbLclkDpm.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbLclkDpm.c
index 5034ed5..8e19a0c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbLclkDpm.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbLclkDpm.c
@@ -231,7 +231,7 @@ NbFmInitLclkDpmRcActivity (
SamplingPeriod[Index] = SamplingPeriod[Index + 1];
SamplingPeriod[Index + 1] = Temp;
}
- IDS_HDT_CONSOLE (GNB_TRACE, "SamplingPeriod[4] - 0x%x SamplingPeriod[5] - 0x%x SamplingPeriod[6] - 0x%x SamplingPeriod[7] - 0x%x \n",
+ IDS_HDT_CONSOLE (GNB_TRACE, "SamplingPeriod[4] - 0x%x SamplingPeriod[5] - 0x%x SamplingPeriod[6] - 0x%x SamplingPeriod[7] - 0x%x\n",
SamplingPeriod[4], SamplingPeriod[5], SamplingPeriod[6], SamplingPeriod[7]
);
NbSmuRcuRegisterWrite (
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.c
index bb9ad5e..343c766 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.c
@@ -304,9 +304,9 @@ NbFuseAdjustFuseTableToCurrentMainPllVco (
EffectiveMainPllFreq10KHz = GfxLibGetMainPllFreq (StdHeader) * 100;
FusedMainPllFreq10KHz = (PpFuseArray->MainPllId + 0x10) * 100 * 100;
if (FusedMainPllFreq10KHz != EffectiveMainPllFreq10KHz) {
- IDS_HDT_CONSOLE (NB_MISC, " WARNING! Adjusting fuse table for reprogrammed VCO \n");
- IDS_HDT_CONSOLE (NB_MISC, " Actual main Freq %d \n", EffectiveMainPllFreq10KHz);
- IDS_HDT_CONSOLE (NB_MISC, " Fused main Freq %d \n", FusedMainPllFreq10KHz);
+ IDS_HDT_CONSOLE (NB_MISC, " WARNING! Adjusting fuse table for reprogrammed VCO\n");
+ IDS_HDT_CONSOLE (NB_MISC, " Actual main Freq %d\n", EffectiveMainPllFreq10KHz);
+ IDS_HDT_CONSOLE (NB_MISC, " Fused main Freq %d\n", FusedMainPllFreq10KHz);
for (Index = 0; Index < 5; Index++) {
if (PpFuseArray->SclkDpmDid[Index] != 0) {
TempVco = GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], FusedMainPllFreq10KHz);
@@ -404,7 +404,7 @@ NbFuseDebugDump (
);
IDS_HDT_CONSOLE (
NB_MISC,
- " SCLK TDP[%d] - 0x%x \n",
+ " SCLK TDP[%d] - 0x%x\n",
Index,
PpFuseArray->SclkDpmTdpLimit[Index]
);
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmLvDdr3.c
index 156ab1e..6727c40 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmLvDdr3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmLvDdr3.c
@@ -235,7 +235,7 @@ MemMLvDdr3PerformanceEnhFinalize (
LibAmdMemFill (NodeCnt, 0, VOLT1_25_ENCODED_VAL + 1, &NBPtr->MemPtr->StdHeader);
if (mmSharedPtr->VoltageMap != VDDIO_DETERMINED) {
Voltage = ParameterPtr->DDR3Voltage;
- IDS_HDT_CONSOLE (MEM_FLOW, "\nSearching for VDDIO that can maximize frequency: \n");
+ IDS_HDT_CONSOLE (MEM_FLOW, "\nSearching for VDDIO that can maximize frequency:\n");
for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
HighestFreq = 0;
// Find out what the highest frequency that can be reached is on this node across different voltage.
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mndct.c
index 5ccc852..5206519 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mndct.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mndct.c
@@ -3322,7 +3322,7 @@ MemNSlot1MaxRdLatTrainClientNb (
// C.Read the DIMM test addresses.
// D.Compare the values read against the pattern written.
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tTrain Slot 1: \n");
+ IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tTrain Slot 1:\n");
MemNSetBitFieldNb (NBPtr, BFSlotSel, 1);
MaxLatDly = (UINT16) (MemNGetBitFieldNb (NBPtr, BFMaxLatency) + 1); // Add 1 to get back to the last passing value
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.c
index 9ae5fe0..eb260d5 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.c
@@ -550,7 +550,7 @@ MemTTrainDQSEdgeDetect (
}
} /// End Chip Select Loop
TechPtr->ChipSel = TechPtr->ChipSel - CsIndex;
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResult : %c %c %c %c %c %c %c %c %c \n",
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResult : %c %c %c %c %c %c %c %c %c\n",
(SweepData.ResultFound & ((UINT16) 1 << (8))) ? ' ':(CurrentResult & ((UINT16) 1 << (8))) ? 'P':'.',
(SweepData.ResultFound & ((UINT16) 1 << (7))) ? ' ':(CurrentResult & ((UINT16) 1 << (7))) ? 'P':'.',
(SweepData.ResultFound & ((UINT16) 1 << (6))) ? ' ':(CurrentResult & ((UINT16) 1 << (6))) ? 'P':'.',
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c
index c2ebc9b..47419aa 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c
@@ -261,7 +261,7 @@ MemTRdPosWithRxEnDlySeeds3 (
IDS_HDT_CONSOLE (MEM_FLOW, "\n\nStart HW RxEn Seedless training\n\n");
// 1. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[1:0][BlockRxDqsLock] = 1.
NBPtr->SetBitField (NBPtr, BFBlockRxDqsLock, 0x0100);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tChip Select: %02x \n", TechPtr->ChipSel);
+ IDS_HDT_CONSOLE (MEM_FLOW, "\tChip Select: %02x\n", TechPtr->ChipSel);
IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n");
IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tRxEn Orig: ");
//
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f14/Proc/Common/S3RestoreState.c
index e8350a3..b0f3166 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/S3RestoreState.c
@@ -437,7 +437,7 @@ S3RestoreStateFromTable (
return AGESA_ERROR;
}
}
- IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore \n");
+ IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore\n");
return AGESA_SUCCESS;
}
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c
index b7aaf22..b7c043e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c
@@ -483,7 +483,7 @@ S3SaveStateSaveInfoOp (
SaveOffsetPtr->OpCode = OpCode;
SaveOffsetPtr->Length = InformationLength;
S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", Information);
+ IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s\n", Information);
);
LibAmdMemCopy (
(UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER),
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
index 5f06eb6..6caf7cf 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
@@ -639,7 +639,7 @@ GfxIntegratedDebugDumpPpTable (
ATOM_PPLIB_STATE_V2 *StatesPtr;
NON_CLOCK_INFO_ARRAY *NonClockInfoArrayPtr;
CLOCK_INFO_ARRAY *ClockInfoArrayPtr;
- IDS_HDT_CONSOLE (GFX_MISC, " < --- Power Play Table ------ > \n");
+ IDS_HDT_CONSOLE (GFX_MISC, " < --- Power Play Table ------ >\n");
IDS_HDT_CONSOLE (GFX_MISC, " Table Revision = %d\n", PpTable->ucDataRevision
);
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c
index 827bd7f..d2d1d94 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c
@@ -231,7 +231,7 @@ NbFmInitLclkDpmRcActivity (
SamplingPeriod[Index] = SamplingPeriod[Index + 1];
SamplingPeriod[Index + 1] = Temp;
}
- IDS_HDT_CONSOLE (GNB_TRACE, "SamplingPeriod[4] - 0x%x SamplingPeriod[5] - 0x%x SamplingPeriod[6] - 0x%x SamplingPeriod[7] - 0x%x \n",
+ IDS_HDT_CONSOLE (GNB_TRACE, "SamplingPeriod[4] - 0x%x SamplingPeriod[5] - 0x%x SamplingPeriod[6] - 0x%x SamplingPeriod[7] - 0x%x\n",
SamplingPeriod[4], SamplingPeriod[5], SamplingPeriod[6], SamplingPeriod[7]
);
NbSmuRcuRegisterWrite (
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c
index 0ae5507..bd5f970 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c
@@ -300,8 +300,8 @@ NbFuseAdjustFuseTableToCurrentMainPllVco (
FusedMainPllFreq10KHz = (PpFuseArray->MainPllId + 0x10) * 100 * 100;
if (FusedMainPllFreq10KHz != EffectiveMainPllFreq10KHz) {
IDS_HDT_CONSOLE (NB_MISC, " WARNING! Adjusting fuse table for reprogrammed VCO\n");
- IDS_HDT_CONSOLE (NB_MISC, " Actual main Freq %d \n", EffectiveMainPllFreq10KHz);
- IDS_HDT_CONSOLE (NB_MISC, " Fused main Freq %d \n", FusedMainPllFreq10KHz);
+ IDS_HDT_CONSOLE (NB_MISC, " Actual main Freq %d\n", EffectiveMainPllFreq10KHz);
+ IDS_HDT_CONSOLE (NB_MISC, " Fused main Freq %d\n", FusedMainPllFreq10KHz);
for (Index = 0; Index < 5; Index++) {
if (PpFuseArray->SclkDpmDid[Index] != 0) {
TempVco = GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], FusedMainPllFreq10KHz);
@@ -399,7 +399,7 @@ NbFuseDebugDump (
);
IDS_HDT_CONSOLE (
NB_MISC,
- " SCLK TDP[%d] - 0x%x \n",
+ " SCLK TDP[%d] - 0x%x\n",
Index,
PpFuseArray->SclkDpmTdpLimit[Index]
);
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c
index f1fa73e..5a2fa69 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c
@@ -548,7 +548,7 @@ MemTTrainDQSEdgeDetect (
}
} /// End Chip Select Loop
TechPtr->ChipSel = TechPtr->ChipSel - CsIndex;
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResult : %c %c %c %c %c %c %c %c %c \n",
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResult : %c %c %c %c %c %c %c %c %c\n",
(SweepData.ResultFound & ((UINT16) 1 << (8))) ? ' ':(CurrentResult & ((UINT16) 1 << (8))) ? 'P':'.',
(SweepData.ResultFound & ((UINT16) 1 << (7))) ? ' ':(CurrentResult & ((UINT16) 1 << (7))) ? 'P':'.',
(SweepData.ResultFound & ((UINT16) 1 << (6))) ? ' ':(CurrentResult & ((UINT16) 1 << (6))) ? 'P':'.',
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c
index 5f00ec5..d2fa7c6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c
@@ -436,7 +436,7 @@ S3RestoreStateFromTable (
return AGESA_ERROR;
}
}
- IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore \n");
+ IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore\n");
return AGESA_SUCCESS;
}
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c
index e4bd926..3be3a6e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c
@@ -482,7 +482,7 @@ S3SaveStateSaveInfoOp (
SaveOffsetPtr->OpCode = OpCode;
SaveOffsetPtr->Length = InformationLength;
S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", (CHAR8 *)Information);
+ IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s\n", (CHAR8 *)Information);
);
LibAmdMemCopy (
(UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER),
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.c
index 2874f3f..1ec9420 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.c
@@ -242,7 +242,7 @@ MemMLvDdr3PerformanceEnhFinalize (
LibAmdMemFill (NodeCnt, 0, VOLT1_25_ENCODED_VAL + 1, &NBPtr->MemPtr->StdHeader);
if (mmSharedPtr->VoltageMap != VDDIO_DETERMINED) {
Voltage = ParameterPtr->DDR3Voltage;
- IDS_HDT_CONSOLE (MEM_FLOW, "\nSearching for VDDIO that can maximize frequency: \n");
+ IDS_HDT_CONSOLE (MEM_FLOW, "\nSearching for VDDIO that can maximize frequency:\n");
for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
HighestFreq = 0;
// Find out what the highest frequency that can be reached is on this node across different voltage.
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mndct.c
index 666e7fd..05d1cd3 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mndct.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mndct.c
@@ -3361,7 +3361,7 @@ MemNSlot1MaxRdLatTrainClientNb (
// C.Read the DIMM test addresses.
// D.Compare the values read against the pattern written.
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tTrain Slot 1: \n");
+ IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tTrain Slot 1:\n");
MemNSetBitFieldNb (NBPtr, BFSlotSel, 1);
MaxLatDly = (UINT16) (MemNGetBitFieldNb (NBPtr, BFMaxLatency) + 1); // Add 1 to get back to the last passing value
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c
index d78a3fc..31ceb5c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c
@@ -555,7 +555,7 @@ MemTTrainDQSEdgeDetect (
}
} /// End Chip Select Loop
TechPtr->ChipSel = TechPtr->ChipSel - CsIndex;
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResult : %c %c %c %c %c %c %c %c %c \n",
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResult : %c %c %c %c %c %c %c %c %c\n",
(SweepData.ResultFound & ((UINT16) 1 << (8))) ? ' ':(CurrentResult & ((UINT16) 1 << (8))) ? 'P':'.',
(SweepData.ResultFound & ((UINT16) 1 << (7))) ? ' ':(CurrentResult & ((UINT16) 1 << (7))) ? 'P':'.',
(SweepData.ResultFound & ((UINT16) 1 << (6))) ? ' ':(CurrentResult & ((UINT16) 1 << (6))) ? 'P':'.',
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrcSeedTrain.c
index 044e0bf..e0065ba 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrcSeedTrain.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrcSeedTrain.c
@@ -256,7 +256,7 @@ MemTRdPosWithRxEnDlySeeds3 (
IDS_HDT_CONSOLE (MEM_FLOW, "\n\nStart HW RxEn Seedless training\n\n");
// 1. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[1:0][BlockRxDqsLock] = 1.
NBPtr->SetBitField (NBPtr, BFBlockRxDqsLock, 0x0100);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tChip Select: %02x \n", TechPtr->ChipSel);
+ IDS_HDT_CONSOLE (MEM_FLOW, "\tChip Select: %02x\n", TechPtr->ChipSel);
IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n");
IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tRxEn Orig: ");
//
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c
index b8716f2..8a2f3af 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c
@@ -435,7 +435,7 @@ S3RestoreStateFromTable (
return AGESA_ERROR;
}
}
- IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore \n");
+ IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore\n");
return AGESA_SUCCESS;
}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c
index eaebdb1..047033e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c
@@ -481,7 +481,7 @@ S3SaveStateSaveInfoOp (
SaveOffsetPtr->OpCode = OpCode;
SaveOffsetPtr->Length = InformationLength;
S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", Information);
+ IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s\n", Information);
);
LibAmdMemCopy (
(UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER),
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c
index 98004f1..20ef2b8 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c
@@ -81,7 +81,7 @@ FchInitEnv (
FCH_DATA_BLOCK *FchParams;
AGESA_STATUS Status;
- IDS_HDT_CONSOLE (FCH_TRACE, " FchInitEnv Enter... \n");
+ IDS_HDT_CONSOLE (FCH_TRACE, " FchInitEnv Enter...\n");
FchParams = FchInitEnvCreatePrivateData (EnvParams);
// Override internal data with IDS (Optional, internal build only)
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitLate.c
index 07606f4..d96aa92 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitLate.c
@@ -76,7 +76,7 @@ FchInitLate (
FCH_DATA_BLOCK *FchParams;
AGESA_STATUS Status;
- IDS_HDT_CONSOLE (FCH_TRACE, " FchInitLate Enter... \n");
+ IDS_HDT_CONSOLE (FCH_TRACE, " FchInitLate Enter...\n");
FchParams = FchInitLoadDataBlock (&LateParams->FchInterface, &LateParams->StdHeader);
Status = FchTaskLauncher (&FchInitLateTaskTable[0], FchParams, TpFchInitLateDispatching);
IDS_HDT_CONSOLE (FCH_TRACE, " FchInitLate Exit... Status = [0x%x]\n", Status);
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitMid.c
index db46655..a4071a8 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitMid.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitMid.c
@@ -74,7 +74,7 @@ FchInitMid (
FCH_DATA_BLOCK *FchParams;
AGESA_STATUS Status;
- IDS_HDT_CONSOLE (FCH_TRACE, " FchInitMid Enter... \n");
+ IDS_HDT_CONSOLE (FCH_TRACE, " FchInitMid Enter...\n");
FchParams = FchInitLoadDataBlock (&MidParams->FchInterface, &MidParams->StdHeader);
Status = FchTaskLauncher (&FchInitMidTaskTable[0], FchParams, TpFchInitMidDispatching);
IDS_HDT_CONSOLE (FCH_TRACE, " FchInitMid Exit... Status = [0x%x]\n", Status);
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLib.c
index ce38ee2..2f31a1f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLib.c
@@ -190,7 +190,7 @@ FchSataDriveDetectionFpga (
StdHeader = LocalCfgPtr->StdHeader;
TRACE ((DMSG_FCH_TRACE, "FCH - Entering sata drive detection procedure\n\n"));
- TRACE ((DMSG_FCH_TRACE, "SATA BAR5 is %X \n", *pBar5));
+ TRACE ((DMSG_FCH_TRACE, "SATA BAR5 is %X\n", *pBar5));
for ( PortNum = 0; PortNum < 4; PortNum++ ) {
ReadMem (*Bar5 + FCH_SATA_BAR5_REG128 + PortNum * 0x80, AccWidthUint32, &SataBarFpgaInfo);
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
index 1bbb397..ba57ab2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
@@ -887,13 +887,13 @@ GfxIntegratedDebugDumpPpTable (
UINT8 SclkIndex;
UINT8 EclkIndex;
- IDS_HDT_CONSOLE (GFX_MISC, " < --- Power Play Table ------ > \n");
+ IDS_HDT_CONSOLE (GFX_MISC, " < --- Power Play Table ------ >\n");
IDS_HDT_CONSOLE (GFX_MISC, " Table Revision = %d\n", PpTable->ucDataRevision);
StateArray = (STATE_ARRAY *) ((UINT8 *) PpTable + PpTable->usStateArrayOffset);
StatesPtr = StateArray->States;
NonClockInfoArrayPtr = (NON_CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usNonClockInfoArrayOffset);
ClockInfoArrayPtr = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usClockInfoArrayOffset);
- IDS_HDT_CONSOLE (GFX_MISC, " < --- SW State Table ---------> \n");
+ IDS_HDT_CONSOLE (GFX_MISC, " < --- SW State Table --------->\n");
for (Index = 0; Index < StateArray->ucNumEntries; Index++) {
IDS_HDT_CONSOLE (GFX_MISC, " State #%d\n", Index + 1
);
@@ -918,7 +918,7 @@ GfxIntegratedDebugDumpPpTable (
IDS_HDT_CONSOLE (GFX_MISC, "\n");
StatesPtr = (ATOM_PPLIB_STATE_V2 *) ((UINT8 *) StatesPtr + sizeof (ATOM_PPLIB_STATE_V2) + StatesPtr->ucNumDPMLevels - 1);
}
- IDS_HDT_CONSOLE (GFX_MISC, " < --- SCLK DPM State Table ---> \n");
+ IDS_HDT_CONSOLE (GFX_MISC, " < --- SCLK DPM State Table --->\n");
for (Index = 0; Index < ClockInfoArrayPtr->ucNumEntries; Index++) {
UINT32 Sclk;
Sclk = ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16);
@@ -947,7 +947,7 @@ GfxIntegratedDebugDumpPpTable (
VceClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD) -
sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD));
- IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE State Table [%d]--> \n", VceStateTable->numEntries);
+ IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE State Table [%d]-->\n", VceStateTable->numEntries);
for (Index = 0; Index < VceStateTable->numEntries; Index++) {
SclkIndex = VceStateTable->entries[Index].ucClockInfoIndex & 0x3F;
EclkIndex = VceStateTable->entries[Index].ucVCEClockInfoIndex;
@@ -970,7 +970,7 @@ GfxIntegratedDebugDumpPpTable (
);
}
}
- IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE Voltage Record Table ---> \n");
+ IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE Voltage Record Table --->\n");
for (Index = 0; Index < VceClockVoltageLimitTable->numEntries; Index++) {
EclkIndex = VceClockVoltageLimitTable->entries[Index].ucVCEClockInfoIndex;
IDS_HDT_CONSOLE (GFX_MISC, " VCE Voltage Record #%d\n", Index
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
index 9737bd2..ccb0043 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
@@ -960,7 +960,7 @@ GnbFuseTableDebugDumpTN (
);
IDS_HDT_CONSOLE (
NB_MISC,
- " SCLK TDP[%d] - 0x%x \n",
+ " SCLK TDP[%d] - 0x%x\n",
Index,
PpFuseArray->SclkDpmTdpLimit[Index]
);
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
index b6b98e0..b2bfa20 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
@@ -252,7 +252,7 @@ GnbIommuIvrsTableDump (
UINT8 *Block;
UINT8 *Entry;
Block = (UINT8 *) Ivrs + sizeof (IOMMU_IVRS_HEADER);
- IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table Start -----------> \n");
+ IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table Start ----------->\n");
IDS_HDT_CONSOLE (GNB_TRACE, " IVInfo = 0x%08x\n", ((IOMMU_IVRS_HEADER *) Ivrs)-> IvInfo);
while (Block < ((UINT8 *) Ivrs + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength)) {
if (*Block == IvrsIvhdBlock) {
@@ -326,9 +326,9 @@ GnbIommuIvrsTableDump (
Block = Block + ((IVRS_IVMD_ENTRY *) Block)->Length;
}
}
- IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table Raw Data --------> \n");
+ IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table Raw Data -------->\n");
GnbLibDebugDumpBuffer (Ivrs, ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength, 1, 16);
IDS_HDT_CONSOLE (GNB_TRACE, "\n");
- IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table End -------------> \n");
+ IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table End ------------->\n");
}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmLvDdr3.c
index 5f64db5..5342420 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmLvDdr3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmLvDdr3.c
@@ -254,7 +254,7 @@ MemMLvDdr3PerformanceEnhFinalize (
LibAmdMemFill (NodeCnt, 0, VOLT1_25_ENCODED_VAL + 1, &NBPtr->MemPtr->StdHeader);
if (mmSharedPtr->VoltageMap != VDDIO_DETERMINED) {
Voltage = ParameterPtr->DDR3Voltage;
- IDS_HDT_CONSOLE (MEM_FLOW, "\nSearching for VDDIO that can maximize frequency: \n");
+ IDS_HDT_CONSOLE (MEM_FLOW, "\nSearching for VDDIO that can maximize frequency:\n");
for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
HighestFreq = 0;
// Find out what the highest frequency that can be reached is on this node across different voltage.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c
index a3b5d76..3b678a8 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c
@@ -3467,7 +3467,7 @@ MemNSlot1MaxRdLatTrainClientNb (
// C.Read the DIMM test addresses.
// D.Compare the values read against the pattern written.
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tTrain Slot 1: \n");
+ IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tTrain Slot 1:\n");
MemNSetBitFieldNb (NBPtr, BFSlotSel, 1);
MaxLatDly = (UINT16) (MemNGetBitFieldNb (NBPtr, BFMaxLatency) + 1); // Add 1 to get back to the last passing value
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c
index 46e591a..8a6a56b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c
@@ -547,7 +547,7 @@ MemTTrainDQSEdgeDetect (
}
} /// End Chip Select Loop
TechPtr->ChipSel = TechPtr->ChipSel - CsIndex;
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResult : %c %c %c %c %c %c %c %c %c \n",
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResult : %c %c %c %c %c %c %c %c %c\n",
(SweepData.ResultFound & ((UINT16) 1 << (8))) ? ' ':(CurrentResult & ((UINT16) 1 << (8))) ? 'P':'.',
(SweepData.ResultFound & ((UINT16) 1 << (7))) ? ' ':(CurrentResult & ((UINT16) 1 << (7))) ? 'P':'.',
(SweepData.ResultFound & ((UINT16) 1 << (6))) ? ' ':(CurrentResult & ((UINT16) 1 << (6))) ? 'P':'.',
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c
index 3406d76..7500f6b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c
@@ -255,7 +255,7 @@ MemTRdPosWithRxEnDlySeeds3 (
IDS_HDT_CONSOLE (MEM_FLOW, "\n\nStart HW RxEn Seedless training\n\n");
// 1. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[1:0][BlockRxDqsLock] = 1.
NBPtr->SetBitField (NBPtr, BFBlockRxDqsLock, 0x0100);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tChip Select: %02x \n", TechPtr->ChipSel);
+ IDS_HDT_CONSOLE (MEM_FLOW, "\tChip Select: %02x\n", TechPtr->ChipSel);
IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n");
IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tRxEn Orig: ");
//
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c
index 9da575c..cc607ba 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c
@@ -435,7 +435,7 @@ S3RestoreStateFromTable (
return AGESA_ERROR;
}
}
- IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore \n");
+ IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore\n");
return AGESA_SUCCESS;
}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c
index c81c877..2b09739 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c
@@ -481,7 +481,7 @@ S3SaveStateSaveInfoOp (
SaveOffsetPtr->OpCode = OpCode;
SaveOffsetPtr->Length = InformationLength;
S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", Information);
+ IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s\n", Information);
);
LibAmdMemCopy (
(UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER),
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitEnv.c
index f1ce3ab..61ec48d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitEnv.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitEnv.c
@@ -80,7 +80,7 @@ FchInitEnv (
FCH_DATA_BLOCK *FchParams;
AGESA_STATUS Status;
- IDS_HDT_CONSOLE (FCH_TRACE, " FchInitEnv Enter... \n");
+ IDS_HDT_CONSOLE (FCH_TRACE, " FchInitEnv Enter...\n");
FchParams = FchInitEnvCreatePrivateData (EnvParams);
// Override internal data with IDS (Optional, internal build only)
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitLate.c
index 1f1bdc1..9f0e1d5 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitLate.c
@@ -75,7 +75,7 @@ FchInitLate (
FCH_DATA_BLOCK *FchParams;
AGESA_STATUS Status;
- IDS_HDT_CONSOLE (FCH_TRACE, " FchInitLate Enter... \n");
+ IDS_HDT_CONSOLE (FCH_TRACE, " FchInitLate Enter...\n");
FchParams = FchInitLoadDataBlock (&LateParams->FchInterface, &LateParams->StdHeader);
Status = FchTaskLauncher (&FchInitLateTaskTable[0], FchParams, TpFchInitLateDispatching);
IDS_HDT_CONSOLE (FCH_TRACE, " FchInitLate Exit... Status = [0x%x]\n", Status);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitMid.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitMid.c
index 50a0849..4127257 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitMid.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitMid.c
@@ -74,7 +74,7 @@ FchInitMid (
FCH_DATA_BLOCK *FchParams;
AGESA_STATUS Status;
- IDS_HDT_CONSOLE (FCH_TRACE, " FchInitMid Enter... \n");
+ IDS_HDT_CONSOLE (FCH_TRACE, " FchInitMid Enter...\n");
FchParams = FchInitLoadDataBlock (&MidParams->FchInterface, &MidParams->StdHeader);
Status = FchTaskLauncher (&FchInitMidTaskTable[0], FchParams, TpFchInitMidDispatching);
IDS_HDT_CONSOLE (FCH_TRACE, " FchInitMid Exit... Status = [0x%x]\n", Status);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataLib.c
index 0b88aa7..30630b5 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataLib.c
@@ -188,7 +188,7 @@ FchSataDriveDetectionFpga (
StdHeader = LocalCfgPtr->StdHeader;
TRACE ((DMSG_FCH_TRACE, "FCH - Entering sata drive detection procedure\n\n"));
- TRACE ((DMSG_FCH_TRACE, "SATA BAR5 is %X \n", *pBar5));
+ TRACE ((DMSG_FCH_TRACE, "SATA BAR5 is %X\n", *pBar5));
for ( PortNum = 0; PortNum < 4; PortNum++ ) {
ReadMem (*Bar5 + FCH_SATA_BAR5_REG128 + PortNum * 0x80, AccWidthUint32, &SataBarFpgaInfo);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c
index 4e83c44..c42d27a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c
@@ -1106,7 +1106,7 @@ GfxPwrPlayBuildTable (
PpWorkspace.PpTable->ATOM_PPLIB_POWERPLAYTABLE4_fld17 =
(USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable));
- IDS_HDT_CONSOLE (GNB_TRACE, "ExtendedHeader \n");
+ IDS_HDT_CONSOLE (GNB_TRACE, "ExtendedHeader\n");
IDS_HDT_CONSOLE (GNB_TRACE, " VceTableOffset = %04x\n", ExtendedHeader->usVCETableOffset);
IDS_HDT_CONSOLE (GNB_TRACE, " UvdTableOffset = %04x\n", ExtendedHeader->usUVDTableOffset);
IDS_HDT_CONSOLE (GNB_TRACE, " SamTableOffset = %04x\n", ExtendedHeader->usSAMUTableOffset);
@@ -1150,13 +1150,13 @@ GfxIntDebugDumpPpTable (
ATOM_PPLIB_SAMCLK_VOLT_LIMIT_TABLE *SamuClockVoltLimitTable;
UINT8 EclkIndex;
- IDS_HDT_CONSOLE (GFX_MISC, " < --- Power Play Table ------ > \n");
+ IDS_HDT_CONSOLE (GFX_MISC, " < --- Power Play Table ------ >\n");
IDS_HDT_CONSOLE (GFX_MISC, " Table Revision = %d\n", PpTable->ucDataRevision);
StateArray = (STATE_ARRAY *) ((UINT8 *) PpTable + PpTable->usStateArrayOffset);
StatesPtr = StateArray->States;
NonClockInfoArrayPtr = (NON_CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usNonClockInfoArrayOffset);
ClockInfoArrayPtr = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usClockInfoArrayOffset);
- IDS_HDT_CONSOLE (GFX_MISC, " < --- SW State Table ---------> \n");
+ IDS_HDT_CONSOLE (GFX_MISC, " < --- SW State Table --------->\n");
for (Index = 0; Index < StateArray->ucNumEntries; Index++) {
IDS_HDT_CONSOLE (GFX_MISC, " State #%d\n", Index + 1
);
@@ -1198,9 +1198,9 @@ GfxIntDebugDumpPpTable (
(ATOM_PPLIB_SAMCLK_VOLT_LIMIT_TABLE *)
((UINT8 *) PpTable + ExtendedHeader->usSAMUTableOffset + sizeof (ATOM_PPLIB_SAMU_TABLE));
- IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE State Table [%d]--> \n", VceStateTable->numEntries);
+ IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE State Table [%d]-->\n", VceStateTable->numEntries);
- IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE Voltage Record Table ---> \n");
+ IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE Voltage Record Table --->\n");
for (Index = 0; Index < VceClockVoltageLimitTable->numEntries; Index++) {
EclkIndex = VceClockVoltageLimitTable->entries[Index].ucVCEClockInfoIndex;
IDS_HDT_CONSOLE (GFX_MISC, " VCE Voltage Record #%d\n", Index
@@ -1214,7 +1214,7 @@ GfxIntDebugDumpPpTable (
}
- IDS_HDT_CONSOLE (GFX_MISC, " < --- SAMU Voltage Record Table ---> \n");
+ IDS_HDT_CONSOLE (GFX_MISC, " < --- SAMU Voltage Record Table --->\n");
for (Index = 0; Index < SamuClockVoltLimitTable->numEntries; Index++) {
IDS_HDT_CONSOLE (GFX_MISC, " SAMU Voltage Record #%d\n", Index
);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c
index c5eb8a1..c716660 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c
@@ -241,7 +241,7 @@ GnbUraStreamSetKB (
switch (UraTokenInfo->MethodType) {
case TYPE_GNB_INDIRECT_ACCESS:
TargetAddress = Device->DevPciAddress.AddressValue | UraTokenInfo->RegDomainType;
- //IDS_HDT_CONSOLE (NB_MISC, "0x%08x:0x%08x, \n", StreamSetAddress, RegValue);
+ //IDS_HDT_CONSOLE (NB_MISC, "0x%08x:0x%08x,\n", StreamSetAddress, RegValue);
GnbLibPciIndirectWrite (TargetAddress, StreamSetAddress, Width, &RegValue, Device->StdHeader);
break;
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c
index b355d6b..04e1ef0 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c
@@ -205,7 +205,7 @@ MemFRdWr2DProgramVrefKB (
//
AGESA_TESTPOINT (TpProcMemBefore2dTrainExtVrefChange, &(NBPtr->MemPtr->StdHeader));
NBPtr->MemPtr->ParameterListPtr->ExternalVrefValue = Vref;
- IDS_HDT_CONSOLE (MEM_FLOW, "\n2D Read Training External CPU Vref Callout \n");
+ IDS_HDT_CONSOLE (MEM_FLOW, "\n2D Read Training External CPU Vref Callout\n");
Va.VoltageType = VTYPE_CPU_VREF;
Va.AdjustValue = Vref = (Vref - 15) << 1;
Status = AgesaExternalVoltageAdjust ((UINTN)CallOutIdInfo.IdInformation, &Va);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c
index 6a9e873..08e4945 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c
@@ -234,7 +234,7 @@ MemFAmdRdWr2DTraining (
}
}
TechPtr->ChipSel = ChipSel;
- IDS_HDT_CONSOLE (MEM_FLOW,"\tChip Select: %02x \n", TechPtr->ChipSel);
+ IDS_HDT_CONSOLE (MEM_FLOW,"\tChip Select: %02x\n", TechPtr->ChipSel);
//
// 1. Sample the data eyes for each channel:
//
@@ -477,7 +477,7 @@ MemFRdWr2DProgramVref (
// External vref control
AGESA_TESTPOINT (TpProcMemBefore2dTrainExtVrefChange, &(NBPtr->MemPtr->StdHeader));
NBPtr->MemPtr->ParameterListPtr->ExternalVrefValue = Vref;
- IDS_HDT_CONSOLE (MEM_FLOW, "\n2D Read Training External CPU Vref Callout \n");
+ IDS_HDT_CONSOLE (MEM_FLOW, "\n2D Read Training External CPU Vref Callout\n");
Va.VoltageType = VTYPE_CPU_VREF;
Va.AdjustValue = Vref = (Vref - 15) << 1;
Status = AgesaExternalVoltageAdjust ((UINTN)CallOutIdInfo.IdInformation, &Va);
@@ -956,7 +956,7 @@ MemFRdWr2DApplyMask (
}
IDS_HDT_CONSOLE_DEBUG_CODE (
IDS_HDT_CONSOLE (MEM_FLOW, "\n");
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t Diamond Shape: \n");
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\t Diamond Shape:\n");
for (Vref = 0; Vref < (NBPtr->TotalMaxVrefRange - 1); Vref++) {
IDS_HDT_CONSOLE (MEM_FLOW, "\n");
for (RdWrDly = (Data->MaxRdWrSweep - Width); RdWrDly < Data->MaxRdWrSweep; RdWrDly++) {
@@ -1360,7 +1360,7 @@ MemFRdWr2DDisplaySearch (
} else {
IDS_HDT_CONSOLE (MEM_FLOW, " ");
}
- IDS_HDT_CONSOLE (MEM_FLOW, "%08x \n", Data->Lane[Lane].Vref[Vref].PosRdWrDly);
+ IDS_HDT_CONSOLE (MEM_FLOW, "%08x\n", Data->Lane[Lane].Vref[Vref].PosRdWrDly);
NBPtr->FamilySpecificHook[Adjust2DVrefStepSize] (NBPtr, &Vref);
}
}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmLvDdr3.c
index ee3eec7..7880cbb 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmLvDdr3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmLvDdr3.c
@@ -250,7 +250,7 @@ MemMLvDdr3PerformanceEnhFinalize (
LibAmdMemFill (NodeCnt, 0, VOLT1_25_ENCODED_VAL + 1, &NBPtr->MemPtr->StdHeader);
if (mmSharedPtr->VoltageMap != VDDIO_DETERMINED) {
Voltage = ParameterPtr->DDR3Voltage;
- IDS_HDT_CONSOLE (MEM_FLOW, "\nSearching for VDDIO that can maximize frequency: \n");
+ IDS_HDT_CONSOLE (MEM_FLOW, "\nSearching for VDDIO that can maximize frequency:\n");
for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
HighestFreq = 0;
// Find out what the highest frequency that can be reached is on this node across different voltage.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c
index 01e63f8..b6a11fe 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c
@@ -547,7 +547,7 @@ MemTTrainDQSEdgeDetect (
}
} /// End Chip Select Loop
TechPtr->ChipSel = TechPtr->ChipSel - CsIndex;
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResult : %c %c %c %c %c %c %c %c %c \n",
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResult : %c %c %c %c %c %c %c %c %c\n",
(SweepData.ResultFound & ((UINT16) 1 << (8))) ? ' ':(CurrentResult & ((UINT16) 1 << (8))) ? 'P':'.',
(SweepData.ResultFound & ((UINT16) 1 << (7))) ? ' ':(CurrentResult & ((UINT16) 1 << (7))) ? 'P':'.',
(SweepData.ResultFound & ((UINT16) 1 << (6))) ? ' ':(CurrentResult & ((UINT16) 1 << (6))) ? 'P':'.',
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c
index a568f9e..bcd9a00 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c
@@ -293,7 +293,7 @@ MemT2DRdDQSEyeRimSearch (
//
// EnableDisable continuous writes on the agressor channels
//
- IDS_HDT_CONSOLE (MEM_FLOW,"\n\tEye Rim Search, ParallelSampling: %c, BroadcastDelays: %c \n", (RimData.ParallelSampling == TRUE) ? 'Y' : 'N', (RimData.BroadcastDelays == TRUE) ? 'Y' : 'N');
+ IDS_HDT_CONSOLE (MEM_FLOW,"\n\tEye Rim Search, ParallelSampling: %c, BroadcastDelays: %c\n", (RimData.ParallelSampling == TRUE) ? 'Y' : 'N', (RimData.BroadcastDelays == TRUE) ? 'Y' : 'N');
for (Aggr = 0; Aggr < (NBPtr->MaxAggressorDimms[(NBPtr->Dct + 1) & 1] > 0 ? NBPtr->MaxAggressorDimms[(NBPtr->Dct + 1) & 1] : 1) ; Aggr += (NBPtr->IsSupported[PerDimmAggressors2D] ? 2 : NBPtr->CsPerDelay) ) {
ClearSampledPassResults (TechPtr);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c
index 0fc13f9..15f6c72 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c
@@ -204,7 +204,7 @@ MemTAmdRdDqs2DTraining (
}
}
TechPtr->ChipSel = ChipSel;
- IDS_HDT_CONSOLE (MEM_FLOW,"\tChip Select: %02x \n", TechPtr->ChipSel);
+ IDS_HDT_CONSOLE (MEM_FLOW,"\tChip Select: %02x\n", TechPtr->ChipSel);
//
// 1. Sample the data eyes for each channel:
//
@@ -389,7 +389,7 @@ MemT2DProgramVref (
// External vref control
AGESA_TESTPOINT (TpProcMemBefore2dTrainExtVrefChange, &(TechPtr->NBPtr->MemPtr->StdHeader));
TechPtr->NBPtr->MemPtr->ParameterListPtr->ExternalVrefValue = Vref;
- IDS_HDT_CONSOLE (MEM_FLOW, "\n2D training External Vref callout \n");
+ IDS_HDT_CONSOLE (MEM_FLOW, "\n2D training External Vref callout\n");
//
/// @todo: Implement UEFI DXE Callout for AgesaExternal2dTrainVrefChange before uncommenting this
//
@@ -820,7 +820,7 @@ MemT2DRdDQSApplyMask (
}
IDS_HDT_CONSOLE_DEBUG_CODE (
IDS_HDT_CONSOLE (MEM_FLOW, "\n");
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t Diamond Shape: \n");
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\t Diamond Shape:\n");
for (Vref = 0; Vref < (NBPtr->TotalMaxVrefRange - 1); Vref++) {
IDS_HDT_CONSOLE (MEM_FLOW, "\n");
for (RdDqsDly = (Data->MaxRdDqsSweep - Width); RdDqsDly < Data->MaxRdDqsSweep; RdDqsDly++) {
@@ -1130,7 +1130,7 @@ MemT2DRdDQSFinalVrefMargin (
}
TechPtr->NBPtr->ChannelPtr->MaxVref = (Data->Vnom - 1) - OffsetFromVref;
}
- IDS_HDT_CONSOLE (MEM_FLOW, "%02x \n", OffsetFromVref);
+ IDS_HDT_CONSOLE (MEM_FLOW, "%02x\n", OffsetFromVref);
MaxRegVref = TechPtr->NBPtr->ChannelPtr->MaxVref;
if (MaxRegVref <= ((TechPtr->NBPtr->TotalMaxVrefRange / 2) - 1)) {
MaxRegVref = (TechPtr->NBPtr->TotalMaxVrefRange - 1) - MaxRegVref;
@@ -1139,7 +1139,7 @@ MemT2DRdDQSFinalVrefMargin (
}
/// @todo: Need Family specific hook for MaxRegVref
MaxRegVref = ((MaxRegVref * 2) & 0x3F);
- IDS_HDT_CONSOLE (MEM_FLOW, "Actual Max Vref programmed = %02x \n", MaxRegVref);
+ IDS_HDT_CONSOLE (MEM_FLOW, "Actual Max Vref programmed = %02x\n", MaxRegVref);
return TRUE;
}
/* -----------------------------------------------------------------------------*/
@@ -1177,7 +1177,7 @@ MemT2DRdDqsDisplaySearch (
IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", Vref - (Data->Vnom - 1));
}
IDS_HDT_CONSOLE (MEM_FLOW, "%08x", TechPtr->Local2DData->Lane[Lane].Vref[Vref].NegRdDqsDly); // debug
- IDS_HDT_CONSOLE (MEM_FLOW, "%08x \n", TechPtr->Local2DData->Lane[Lane].Vref[Vref].PosRdDqsDly); //debug
+ IDS_HDT_CONSOLE (MEM_FLOW, "%08x\n", TechPtr->Local2DData->Lane[Lane].Vref[Vref].PosRdDqsDly); //debug
TechPtr->NBPtr->FamilySpecificHook[Adjust2DVrefStepSize] (TechPtr->NBPtr, &Vref);
}
}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
index ce295ac..af4d590 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
@@ -255,7 +255,7 @@ MemTRdPosWithRxEnDlySeeds3 (
IDS_HDT_CONSOLE (MEM_FLOW, "\n\nStart HW RxEn Seedless training\n\n");
// 1. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[1:0][BlockRxDqsLock] = 1.
NBPtr->SetBitField (NBPtr, BFBlockRxDqsLock, 0x0100);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tChip Select: %02x \n", TechPtr->ChipSel);
+ IDS_HDT_CONSOLE (MEM_FLOW, "\tChip Select: %02x\n", TechPtr->ChipSel);
IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n");
IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tRxEn Orig: ");
//
diff --git a/src/vendorcode/amd/cimx/rd890/nbDispatcher.c b/src/vendorcode/amd/cimx/rd890/nbDispatcher.c
index 16e86a1..1b430c4 100644
--- a/src/vendorcode/amd/cimx/rd890/nbDispatcher.c
+++ b/src/vendorcode/amd/cimx/rd890/nbDispatcher.c
@@ -82,7 +82,7 @@ AmdNbDispatcher (
ImageEntry = NULL;
Status = AGESA_UNSUPPORTED;
CIMX_INIT_TRACE ((ConfigPtr));
- CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_TRACE_ALL), "CIMx - RD890 Entry \n"));
+ CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_TRACE_ALL), "CIMx - RD890 Entry\n"));
CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_TRACE_ALL), " Funcid = %x Callout = %x\n", ((AMD_CONFIG_PARAMS*)ConfigPtr)->Func, ((AMD_CONFIG_PARAMS*)ConfigPtr)->CalloutPtr));
#ifdef B1_IMAGE
@@ -192,7 +192,7 @@ AmdNbDispatcher (
// 4. Try next dispatcher if possible, and we have not already got status back
if ((mNbModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {
MODULE_ENTRY ModuleEntry;
- CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_TRACE_ALL), "CIMx - RD890 control goes to next Module \n"));
+ CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_TRACE_ALL), "CIMx - RD890 control goes to next Module\n"));
ModuleEntry = mNbModuleID.NextBlock->ModuleDispatcher;
Status = (*ModuleEntry) (ConfigPtr);
}
diff --git a/src/vendorcode/amd/cimx/rd890/nbIoApic.c b/src/vendorcode/amd/cimx/rd890/nbIoApic.c
index 045883d..3867b80 100644
--- a/src/vendorcode/amd/cimx/rd890/nbIoApic.c
+++ b/src/vendorcode/amd/cimx/rd890/nbIoApic.c
@@ -177,7 +177,7 @@ NbLibSetIOAPIC (
(PortInfo.Pin) << RegisterInfo.RcRoutingOffset,
pConfig
);
- CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NB_TRACE), " RC Routing Dev[%d] NativeDev[%d] Pin - %d \n", Port.Address.Device, NativePortId, PortInfo.Pin));
+ CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NB_TRACE), " RC Routing Dev[%d] NativeDev[%d] Pin - %d\n", Port.Address.Device, NativePortId, PortInfo.Pin));
}
LibNbPciIndexRMW (
diff --git a/src/vendorcode/amd/cimx/rd890/nbIommu.c b/src/vendorcode/amd/cimx/rd890/nbIommu.c
index 705b1a8..24d2a1a 100644
--- a/src/vendorcode/amd/cimx/rd890/nbIommu.c
+++ b/src/vendorcode/amd/cimx/rd890/nbIommu.c
@@ -830,7 +830,7 @@ IommuInitL2CacheControl (
NBits = NBits - NFuncBits;
NDevBits = CIMX_MIN ( NBits, DevBitsUsed + FuncBitsUsed - NFuncBits);
NBusBits = NBits - NDevBits;
- CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NB_TRACE), " NBusBits = %d, NDevBits = %d, NFuncBits = %d \n", NBusBits, NDevBits, NFuncBits));
+ CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NB_TRACE), " NBusBits = %d, NDevBits = %d, NFuncBits = %d\n", NBusBits, NDevBits, NFuncBits));
LibNbPciIndexRMW (
IommuPciAddress.AddressValue | L2CFG_INDEX,
L2CFG_SEL_WR_EN | (HashControls[i].HashControl + 1),
diff --git a/src/vendorcode/amd/cimx/rd890/nbLib.c b/src/vendorcode/amd/cimx/rd890/nbLib.c
index 5862768..c253ca2 100644
--- a/src/vendorcode/amd/cimx/rd890/nbLib.c
+++ b/src/vendorcode/amd/cimx/rd890/nbLib.c
@@ -1027,7 +1027,7 @@ LibNbScanPciBridgeBuses (
if (MinBus == 0 || MaxBus == 0) {
return SCAN_FINISHED;
}
- CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (This->pConfig), CIMX_NBPCIE_TRACE), " Scan bridge %d:%d:%d \n", Bridge.Address.Bus, Bridge.Address.Device, Bridge.Address.Function));
+ CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (This->pConfig), CIMX_NBPCIE_TRACE), " Scan bridge %d:%d:%d\n", Bridge.Address.Bus, Bridge.Address.Device, Bridge.Address.Function));
for (CurrentBus = MinBus; CurrentBus <= MaxBus; CurrentBus++) {
Device.AddressValue = MAKE_SBDFO (0, CurrentBus, 0, 0, 0);
Status = This->ScanBus (This, Device);
@@ -1101,7 +1101,7 @@ LibNbScanPciDevice (
for (CurrentFunction = Device.Address.Function; CurrentFunction <= MaxFunction; CurrentFunction++) {
Device.Address.Function = CurrentFunction;
if (LibNbIsDevicePresent (Device, This->pConfig)) {
- CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (This->pConfig), CIMX_NBPCIE_TRACE), " Scan function %d:%d:%d \n", Device.Address.Bus, Device.Address.Device, Device.Address.Function));
+ CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (This->pConfig), CIMX_NBPCIE_TRACE), " Scan function %d:%d:%d\n", Device.Address.Bus, Device.Address.Device, Device.Address.Function));
Status = This->ScanFunction (This, Device);
if (Status == SCAN_STOP_DEVICE_ENUMERATION || Status == SCAN_STOP_BUS_ENUMERATION) {
return Status;
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieAspm.c b/src/vendorcode/amd/cimx/rd890/nbPcieAspm.c
index 38bc41f..9599da3 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPcieAspm.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieAspm.c
@@ -462,7 +462,7 @@ PcieSetDeviceAspm (
This->ScanBus (This, DownstreamDevice);
} else if (DeviceType < PcieDeviceLegacyEndPoint) {
// We reach end of link @toDo code to check exit latency.
- CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (This->pConfig), CIMX_NBPCIE_TRACE), " Reached endpoint \n"));
+ CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (This->pConfig), CIMX_NBPCIE_TRACE), " Reached endpoint\n"));
}
return SCAN_FINISHED;
}
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieInitEarly.c b/src/vendorcode/amd/cimx/rd890/nbPcieInitEarly.c
index 6fdf2b1..268c631 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPcieInitEarly.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieInitEarly.c
@@ -694,8 +694,8 @@ PcieGetPortsLinkStatus (
//Get link state
LibNbPciIndexRead (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGA5, AccessWidth32, &LinkState, pConfig);
LinkState &= 0x3F;
- //CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_MISC), " PortId %d LinkState = 0x%x \n", PortId, LinkState));
- printk(BIOS_INFO, "[NBPCIE] PortId %02d LinkState = 0x%x \n", PortId, LinkState);
+ //CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_MISC), " PortId %d LinkState = 0x%x\n", PortId, LinkState));
+ printk(BIOS_INFO, "[NBPCIE] PortId %02d LinkState = 0x%x\n", PortId, LinkState);
//Check if link in L0 state
if (LinkState == 0x10) {
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c b/src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c
index 17ae4f7..856c81d 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c
@@ -388,10 +388,10 @@ PcieInitiateSoftwareGen2 (
LibNbPciRead (Port.AddressValue | NB_PCIP_REG19, AccessWidth8, &SecondaryBus, pConfig);
Ep.AddressValue = 0;
Ep.Address.Bus = SecondaryBus;
- CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE] SecondaryBus = 0x%x \n", SecondaryBus));
+ CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE] SecondaryBus = 0x%x\n", SecondaryBus));
PcieCapPtr = LibNbFindPciCapability (Ep.AddressValue, PCIE_CAP_ID, pConfig);
LibNbPciRead (Ep.AddressValue | (PcieCapPtr + 0xC), AccessWidth8, &LinkSpeedCap, pConfig);
- CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE] PcieCapPtr = 0x%x \n", PcieCapPtr));
+ CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE] PcieCapPtr = 0x%x\n", PcieCapPtr));
if ((LinkSpeedCap & 0xf) < 2) {
return;
}
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieLateHwLib.c b/src/vendorcode/amd/cimx/rd890/nbPcieLateHwLib.c
index 8b1782e..5c5a85c 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPcieLateHwLib.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieLateHwLib.c
@@ -221,7 +221,7 @@ PcieLibManageLclkClock (
UINT32 CoreAddress;
PCIE_CONFIG *pPcieConfig;
- CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibManageLclkClock [CoreId %d] Enter \n", CoreId));
+ CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibManageLclkClock [CoreId %d] Enter\n", CoreId));
pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
ClkPciAddress = pConfig->NbPciAddress;
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieLib.c b/src/vendorcode/amd/cimx/rd890/nbPcieLib.c
index 2e91cb6..a6a5be5 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPcieLib.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieLib.c
@@ -512,7 +512,7 @@ PcieLibSetCoreConfiguration (
(pCoreInfo->PortIdBitMap & (1 << PortId)) != 0) {
PORT_STATIC_INFO *pStaticPortInfo = PcieLibGetStaticPortInfo (PcieLibNativePortId (PortId, pConfig), pConfig);
LaneReversalValue |= (1 << (pStaticPortInfo->ReversalAddress));
- CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " Port reversed Port Id %d Native Id %d, Reversal Address %d \n", PortId, PcieLibNativePortId (PortId, pConfig), pStaticPortInfo->ReversalAddress));
+ CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " Port reversed Port Id %d Native Id %d, Reversal Address %d\n", PortId, PcieLibNativePortId (PortId, pConfig), pStaticPortInfo->ReversalAddress));
}
}
}
@@ -1154,7 +1154,7 @@ PcieLibValidateGfxConfig (
CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibValidateGfxConfig Enter\n"));
CoreId = PcieLibGetCoreId (PortId, pConfig);
pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
- CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " CoreConfiguration[%d] = \n", CoreId));
+ CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), " CoreConfiguration[%d] =\n", CoreId));
if (pPcieConfig->CoreConfiguration[CoreId] == 0x0) {
pPcieConfig->CoreConfiguration[CoreId] = (pPcieConfig->PortConfiguration[PortId].PortPresent == ON)?GFX_CONFIG_AABB:GFX_CONFIG_AAAA;
} else {
diff --git a/src/vendorcode/amd/cimx/rd890/nbPciePllControl.c b/src/vendorcode/amd/cimx/rd890/nbPciePllControl.c
index ec2206b..a2f2c46 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPciePllControl.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPciePllControl.c
@@ -185,7 +185,7 @@ PciePllOffCheckFunction (
if (WorkspacePtr->MaxL1Latency < L1AcceptableLatency) {
WorkspacePtr->MaxL1Latency = L1AcceptableLatency;
}
- CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (This->pConfig), CIMX_NBPCIE_TRACE), " Reached end of link at 0x%x with Acceptable Exit Latency %dus \n", Function.AddressValue, L1AcceptableLatency));
+ CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (This->pConfig), CIMX_NBPCIE_TRACE), " Reached end of link at 0x%x with Acceptable Exit Latency %dus\n", Function.AddressValue, L1AcceptableLatency));
}
}
}
diff --git a/src/vendorcode/amd/cimx/rd890/nbPciePortRemap.c b/src/vendorcode/amd/cimx/rd890/nbPciePortRemap.c
index 639f149..43a3ba4 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPciePortRemap.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPciePortRemap.c
@@ -95,7 +95,7 @@ PciePortRemapInit (
PORT PortId;
PCIE_CONFIG *pPcieConfig;
- CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PciePortDeviceNumberRemap Enter \n"));
+ CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PciePortDeviceNumberRemap Enter\n"));
pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
Status = AGESA_SUCCESS;
IsDeviceRemapEnabled = FALSE;
@@ -151,7 +151,7 @@ PciePortRemapInit (
}
LibNbPciIndexRMW (NB_SBDFO | NB_MISC_INDEX, NB_MISC_REG20, AccessWidth32, 0xffffffff, 0x3, pConfig);
- CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PciePortDeviceNumberRemap Exit [0x%x] \n", Status));
+ CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PciePortDeviceNumberRemap Exit [0x%x]\n", Status));
return Status;
}
diff --git a/src/vendorcode/amd/cimx/sb700/AZALIA.c b/src/vendorcode/amd/cimx/sb700/AZALIA.c
index cc72858..80f03a4 100644
--- a/src/vendorcode/amd/cimx/sb700/AZALIA.c
+++ b/src/vendorcode/amd/cimx/sb700/AZALIA.c
@@ -151,7 +151,7 @@ void azaliaInitAfterPciEnum (AMDSBCFG* pConfig){
if (ddBAR0 != 0xFFFFFFFF){
ddBAR0 &= ~(0x03FFF);
dbEnableAzalia = 1;
- TRACE((DMSG_SB_TRACE, "CIMxSB - Enabling Azalia controller (BAR setup is ok) \n"));
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Enabling Azalia controller (BAR setup is ok)\n"));
}
}
}
@@ -184,7 +184,7 @@ void azaliaInitAfterPciEnum (AMDSBCFG* pConfig){
Stall(1000);
ReadMEM( ddBAR0+SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable);
if (dwTempVariable & 0x0F){
- TRACE((DMSG_SB_TRACE, "CIMxSB - Atleast One Azalia CODEC found \n"));
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Atleast One Azalia CODEC found\n"));
//atleast one azalia codec found
ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8, &dbPinRouting);
do{
@@ -195,7 +195,7 @@ void azaliaInitAfterPciEnum (AMDSBCFG* pConfig){
} while (dbChannelNum != 4);
}
else{
- TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC NOT found \n"));
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC NOT found\n"));
//No Azalia codec found
if (pConfig->AzaliaController != 2)
dbEnableAzalia = 0; //set flag to disable Azalia
@@ -245,7 +245,7 @@ void configureAzaliaPinCmd (AMDSBCFG* pConfig, UINT32 ddBAR0, UINT8 dbChannelNum
else
ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->pAzaliaOemCodecTablePtr;
- TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC table pointer is %x \n", (UINT32)ptempAzaliaOemCodecTablePtr));
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC table pointer is %x\n", (UINT32)ptempAzaliaOemCodecTablePtr));
while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF){
if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable)
@@ -255,9 +255,9 @@ void configureAzaliaPinCmd (AMDSBCFG* pConfig, UINT32 ddBAR0, UINT8 dbChannelNum
}
if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF){
- TRACE((DMSG_SB_TRACE, "CIMxSB - Matching CODEC ID found \n"));
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Matching CODEC ID found\n"));
tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr;
- TRACE((DMSG_SB_TRACE, "CIMxSB - Matching Azalia CODEC table pointer is %x \n", (UINT32)tempAzaliaCodecEntryPtr));
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Matching Azalia CODEC table pointer is %x\n", (UINT32)tempAzaliaCodecEntryPtr));
if ( ((pConfig->pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) 0xFFFFFFFF)) )
tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR(tempAzaliaCodecEntryPtr);
diff --git a/src/vendorcode/amd/cimx/sb700/FLASH.c b/src/vendorcode/amd/cimx/sb700/FLASH.c
index 0d84245..300a2b9 100644
--- a/src/vendorcode/amd/cimx/sb700/FLASH.c
+++ b/src/vendorcode/amd/cimx/sb700/FLASH.c
@@ -33,7 +33,7 @@
void fcInitBeforePciEnum(AMDSBCFG* pConfig){
- TRACE((DMSG_SB_TRACE, "Entering PreInit Flash \n"));
+ TRACE((DMSG_SB_TRACE, "Entering PreInit Flash\n"));
RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT1, 00);
//Enable IDE and disable flash
diff --git a/src/vendorcode/amd/cimx/sb700/SATA.c b/src/vendorcode/amd/cimx/sb700/SATA.c
index d503239..3b62e12 100644
--- a/src/vendorcode/amd/cimx/sb700/SATA.c
+++ b/src/vendorcode/amd/cimx/sb700/SATA.c
@@ -241,7 +241,7 @@ void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5){
UINT32 dwIoBase, dwVar0;
TRACE((DMSG_SB_TRACE, "CIMx - Entering sata drive detection procedure\n\n"));
- TRACE((DMSG_SB_TRACE, "SATA BAR5 is %X \n", ddBar5));
+ TRACE((DMSG_SB_TRACE, "SATA BAR5 is %X\n", ddBar5));
if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) ){
for (dbPortNum=0;dbPortNum<4;dbPortNum++){
@@ -416,7 +416,7 @@ void shutdownUnconnectedSataPortClock(AMDSBCFG* pConfig, UINT32 ddBar5){
if (ClockOffEnabled) {
//Shutdown the clock for the port and do the necessary port reporting changes.
- TRACE((DMSG_SB_TRACE, "Shutting down clock for SATA ports %X \n", UnusedPortBitMap));
+ TRACE((DMSG_SB_TRACE, "Shutting down clock for SATA ports %X\n", UnusedPortBitMap));
RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, UnusedPortBitMap);
RWMEM(ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~UnusedPortBitMap, 00);
}
diff --git a/src/vendorcode/amd/cimx/sb700/SBCMN.c b/src/vendorcode/amd/cimx/sb700/SBCMN.c
index 7d5b4f4..5b9b3a3 100644
--- a/src/vendorcode/amd/cimx/sb700/SBCMN.c
+++ b/src/vendorcode/amd/cimx/sb700/SBCMN.c
@@ -134,7 +134,7 @@ void commonInitEarlyBoot(AMDSBCFG* pConfig) {
UINT32 ddValue;
UINT8 Family, Model, Stepping;
- TRACE((DMSG_SB_TRACE, "CIMx - Entering commonInitEarlyBoot \n"));
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering commonInitEarlyBoot\n"));
CpuidRead (0x01, &CpuId);
CpuidRead (0x80000001, &CpuId_Brand); //BrandID
@@ -272,7 +272,7 @@ void commonInitEarlyBoot(AMDSBCFG* pConfig) {
c3PopupSetting(pConfig);
- TRACE((DMSG_SB_TRACE, "CIMx - Exiting commonInitEarlyBoot \n"));
+ TRACE((DMSG_SB_TRACE, "CIMx - Exiting commonInitEarlyBoot\n"));
}
@@ -385,7 +385,7 @@ void abcfgTbl(ABTBLENTRY* pABTbl){
UINT32 ddValue;
while ((pABTbl->regType) != 0xFF){
- TRACE((DMSG_SB_TRACE, "RegType: %X, RegNumber:%X, AndMask=%X, OrMask=%X \n",pABTbl->regType , pABTbl->regIndex, pABTbl->regMask, pABTbl->regData));
+ TRACE((DMSG_SB_TRACE, "RegType: %X, RegNumber:%X, AndMask=%X, OrMask=%X\n",pABTbl->regType , pABTbl->regIndex, pABTbl->regMask, pABTbl->regData));
if (pABTbl->regType > AX_INDXP){
ddValue = pABTbl->regIndex | (pABTbl->regType << 30);
writeAlink(ddValue, ((readAlink(ddValue)) & (0xFFFFFFFF^(pABTbl->regMask)))|pABTbl->regData);
diff --git a/src/vendorcode/amd/cimx/sb700/SBMAIN.c b/src/vendorcode/amd/cimx/sb700/SBMAIN.c
index 7468eb2..219c04f 100644
--- a/src/vendorcode/amd/cimx/sb700/SBMAIN.c
+++ b/src/vendorcode/amd/cimx/sb700/SBMAIN.c
@@ -103,7 +103,7 @@ void sbBeforePciInit (AMDSBCFG* pConfig){
BUILDPARAM *pStaticOptions;
pStaticOptions = &pConfig->BuildParameters;
- TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciInit \n"));
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciInit\n"));
commonInitEarlyBoot(pConfig);
commonInitEarlyPost(pConfig);
#ifndef NO_EC_SUPPORT
@@ -114,7 +114,7 @@ void sbBeforePciInit (AMDSBCFG* pConfig){
sataInitBeforePciEnum(pConfig); // Init SATA class code and PHY
programSubSystemIDs(pConfig, pStaticOptions); // Set subsystem/vendor ID
- TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbBeforePciInit \n"));
+ TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbBeforePciInit\n"));
}
@@ -134,7 +134,7 @@ void sbBeforePciInit (AMDSBCFG* pConfig){
void sbAfterPciInit(AMDSBCFG* pConfig){
BUILDPARAM *pStaticOptions;
- TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciInit \n"));
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciInit\n"));
pStaticOptions = &pConfig->BuildParameters;
usbInitMidPost(pConfig); //usb initialization which is required only during post
@@ -142,7 +142,7 @@ void sbAfterPciInit(AMDSBCFG* pConfig){
sataInitAfterPciEnum(pConfig); // SATA port enumeration
azaliaInitAfterPciEnum(pConfig); // Detect and configure High Definition Audio
- TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbAfterPciInit \n"));
+ TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbAfterPciInit\n"));
}
@@ -163,7 +163,7 @@ void sbLatePost(AMDSBCFG* pConfig){
UINT16 dwVar;
BUILDPARAM *pStaticOptions;
pStaticOptions = &pConfig->BuildParameters;
- TRACE((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n"));
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbLatePost\n"));
ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG02, AccWidthUint16, &dwVar);
if (dwVar != SB7XX_DEVICE_ID){
// Display message that the SB is wrong and stop the system
@@ -194,7 +194,7 @@ void sbLatePost(AMDSBCFG* pConfig){
void sbBeforePciRestoreInit(AMDSBCFG* pConfig){
BUILDPARAM *pStaticOptions;
- TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciRestoreInit \n"));
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciRestoreInit\n"));
pConfig->S3Resume = 1;
@@ -227,7 +227,7 @@ void sbAfterPciRestoreInit(AMDSBCFG* pConfig){
pConfig->S3Resume = 1;
pStaticOptions = &pConfig->BuildParameters;
- TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit \n"));
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit\n"));
commonInitLateBoot(pConfig);
sataInitAfterPciEnum(pConfig);
diff --git a/src/vendorcode/amd/cimx/sb700/SBPOR.c b/src/vendorcode/amd/cimx/sb700/SBPOR.c
index 6c5740b..dd07cdc 100644
--- a/src/vendorcode/amd/cimx/sb700/SBPOR.c
+++ b/src/vendorcode/amd/cimx/sb700/SBPOR.c
@@ -133,7 +133,7 @@ void sbPowerOnInit (AMDSBCFG *pConfig){
UINT16 dwTempVar;
BUILDPARAM *pBuildOptPtr;
- TRACE((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n"));
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit\n"));
setRevisionID();
ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwTempVar);
diff --git a/src/vendorcode/amd/cimx/sb700/SMM.c b/src/vendorcode/amd/cimx/sb700/SMM.c
index 0d752fb..3166262 100644
--- a/src/vendorcode/amd/cimx/sb700/SMM.c
+++ b/src/vendorcode/amd/cimx/sb700/SMM.c
@@ -64,13 +64,13 @@ void sbSmmService(AMDSBCFG* pConfig){
SMM_SERVICE_ROUTINE serviceRoutine;
pSmmItems = (SMMSERVICESTRUC *)FIXUP_PTR(&smmItemsTable[0]);
- TRACE((DMSG_SB_TRACE, "CIMx - Entering SMM services \n"));
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering SMM services\n"));
for (i = 1; i <= (sizeof(smmItemsTable)/sizeof(SMMSERVICESTRUC)); i++){
dbEnableValue = pSmmItems->enableRegNum;
ReadPMIO(pSmmItems->enableRegNum, AccWidthUint8, &dbEnableValue);
ReadPMIO(pSmmItems->statusRegNum, AccWidthUint8, &dbStatusValue);
if ( (dbEnableValue & (pSmmItems->enableBit)) && (dbStatusValue & (pSmmItems->statusBit)) ){
- TRACE((DMSG_SB_TRACE, "\n \nSmi source is: %s \n", pSmmItems->debugMessage));
+ TRACE((DMSG_SB_TRACE, "\n \nSmi source is: %s\n", pSmmItems->debugMessage));
TRACE((DMSG_SB_TRACE, "Enable Reg:%d Value:%d\n", pSmmItems->enableRegNum, dbEnableValue));
TRACE((DMSG_SB_TRACE, "Status Reg:%d Value:%d\n\n", pSmmItems->statusRegNum, dbStatusValue));
if ( (pSmmItems->serviceRoutine)!= NULL){
@@ -79,7 +79,7 @@ void sbSmmService(AMDSBCFG* pConfig){
}
}
}
- TRACE((DMSG_SB_TRACE, "CIMx - Exiting SMM services \n"));
+ TRACE((DMSG_SB_TRACE, "CIMx - Exiting SMM services\n"));
}
@@ -87,5 +87,5 @@ void softwareSMIservice(void){
UINT16 dwSmiCmdPort, dwVar;
ReadPMIO(SB_PMIO_REG2A, AccWidthUint16, &dwSmiCmdPort);
ReadIO(dwSmiCmdPort, AccWidthUint16, &dwVar);
- TRACE((DMSG_SB_TRACE, "SMI CMD Port Address: %X SMICMD Port value is %X \n", dwSmiCmdPort, dwVar));
+ TRACE((DMSG_SB_TRACE, "SMI CMD Port Address: %X SMICMD Port value is %X\n", dwSmiCmdPort, dwVar));
}
diff --git a/src/vendorcode/amd/cimx/sb700/USB.c b/src/vendorcode/amd/cimx/sb700/USB.c
index 9c5e7b3..73798f1 100644
--- a/src/vendorcode/amd/cimx/sb700/USB.c
+++ b/src/vendorcode/amd/cimx/sb700/USB.c
@@ -35,7 +35,7 @@
void usbInitBeforePciEnum(AMDSBCFG* pConfig){
UINT8 dbVar=0;
- TRACE((DMSG_SB_TRACE, "Entering PreInit Usb \n"));
+ TRACE((DMSG_SB_TRACE, "Entering PreInit Usb\n"));
if (pConfig->Usb1Ohci0){
dbVar = (pConfig->Usb1Ehci << 2);
dbVar |= ((pConfig->Usb1Ohci0) << 0);
diff --git a/src/vendorcode/amd/cimx/sb900/Azalia.c b/src/vendorcode/amd/cimx/sb900/Azalia.c
index 9a32018..41b0aa9 100644
--- a/src/vendorcode/amd/cimx/sb900/Azalia.c
+++ b/src/vendorcode/amd/cimx/sb900/Azalia.c
@@ -290,7 +290,7 @@ azaliaInitAfterPciEnum (
if ( ddBAR0 != 0xFFFFFFFF ) {
ddBAR0 &= ~(0x03FFF);
dbEnableAzalia = 1;
- TRACE ((DMSG_SB_TRACE, "CIMxSB - Enabling Azalia controller (BAR setup is ok) \n"));
+ TRACE ((DMSG_SB_TRACE, "CIMxSB - Enabling Azalia controller (BAR setup is ok)\n"));
}
}
}
@@ -354,7 +354,7 @@ azaliaInitAfterPciEnum (
ReadMEM ( ddBAR0 + SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable);
if ( dwTempVariable & 0x0F ) {
- TRACE ((DMSG_SB_TRACE, "CIMxSB - At least One Azalia CODEC found \n"));
+ TRACE ((DMSG_SB_TRACE, "CIMxSB - At least One Azalia CODEC found\n"));
//atleast one azalia codec found
dbPinRouting = pConfig->AZALIACONFIG.AzaliaSdinPin;
do {
@@ -365,7 +365,7 @@ azaliaInitAfterPciEnum (
dbChannelNum++;
} while ( dbChannelNum != 4 );
} else {
- TRACE ((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC NOT found \n"));
+ TRACE ((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC NOT found\n"));
//No Azalia codec found
if ( pConfig->AzaliaController != 2 ) {
dbEnableAzalia = 0; //set flag to disable Azalia
@@ -434,7 +434,7 @@ configureAzaliaPinCmd (
ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr;
}
- TRACE ((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC table pointer is %X \n", ptempAzaliaOemCodecTablePtr));
+ TRACE ((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC table pointer is %X\n", ptempAzaliaOemCodecTablePtr));
while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) {
if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable ) {
@@ -445,9 +445,9 @@ configureAzaliaPinCmd (
}
if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) {
- TRACE ((DMSG_SB_TRACE, "CIMxSB - Matching CODEC ID found \n"));
+ TRACE ((DMSG_SB_TRACE, "CIMxSB - Matching CODEC ID found\n"));
tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr;
- TRACE ((DMSG_SB_TRACE, "CIMxSB - Matching Azalia CODEC table pointer is %X \n", tempAzaliaCodecEntryPtr));
+ TRACE ((DMSG_SB_TRACE, "CIMxSB - Matching Azalia CODEC table pointer is %X\n", tempAzaliaCodecEntryPtr));
if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF)) ) {
tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (tempAzaliaCodecEntryPtr);
diff --git a/src/vendorcode/amd/cimx/sb900/Sata.c b/src/vendorcode/amd/cimx/sb900/Sata.c
index 9d1655c..643acff 100644
--- a/src/vendorcode/amd/cimx/sb900/Sata.c
+++ b/src/vendorcode/amd/cimx/sb900/Sata.c
@@ -181,7 +181,7 @@ shutdownUnconnectedSataPortClock (
// ?? Error port status should be 1 not 3
ddPortSataStatus &= 0x00000F0F;
if ( (!((ddPortSataStatus == 0x601) || (ddPortSataStatus == 0x201) || (ddPortSataStatus == 0x103))) && (! ((pConfig->SATAESPPORT.SataPortReg) & (1 << dbPortNum))) ) {
- TRACE ((DMSG_SB_TRACE, "Shutting down clock for SATA port %X \n", dbPortNum));
+ TRACE ((DMSG_SB_TRACE, "Shutting down clock for SATA port %X\n", dbPortNum));
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, (1 << dbPortNum));
}
} //end of for (dbPortNum=0;dbPortNum<6;dbPortNum++)
@@ -882,7 +882,7 @@ sataDriveDetection (
UINT16 dwIoBase;
UINT32 ddVar1;
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sata drive detection procedure\n\n"));
- TRACE ((DMSG_SB_TRACE, "SATA BAR5 is %X \n", *pBar5));
+ TRACE ((DMSG_SB_TRACE, "SATA BAR5 is %X\n", *pBar5));
if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) ) {
for ( dbPortNum = 0; dbPortNum < 4; dbPortNum++ ) {
ReadMEM (*pBar5 + SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);
@@ -933,7 +933,7 @@ sataDriveDetectionFpga (
UINT16 dwIoBase;
UINT32 ddVar1;
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sata drive detection procedure\n\n"));
- TRACE ((DMSG_SB_TRACE, "SATA BAR5 is %X \n", *pBar5));
+ TRACE ((DMSG_SB_TRACE, "SATA BAR5 is %X\n", *pBar5));
for ( dbPortNum = 0; dbPortNum < 4; dbPortNum++ ) {
ReadMEM (*pBar5 + SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);
if ( ( ddVar0 & 0x0F ) == 0x03 ) {
diff --git a/src/vendorcode/amd/cimx/sb900/SbCmn.c b/src/vendorcode/amd/cimx/sb900/SbCmn.c
index 1767ea1..f70c42e 100644
--- a/src/vendorcode/amd/cimx/sb900/SbCmn.c
+++ b/src/vendorcode/amd/cimx/sb900/SbCmn.c
@@ -388,7 +388,7 @@ commonInitEarlyBoot (
}
- TRACE ((DMSG_SB_TRACE, "CIMx - Entering commonInitEarlyBoot \n"));
+ TRACE ((DMSG_SB_TRACE, "CIMx - Entering commonInitEarlyBoot\n"));
CpuidRead (0x01, &CpuId);
//
@@ -529,7 +529,7 @@ commonInitEarlyBoot (
} else {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD2, AccWidthUint8, ~ (BIT3), 0);
}
- TRACE ((DMSG_SB_TRACE, "CIMx - Exiting commonInitEarlyBoot \n"));
+ TRACE ((DMSG_SB_TRACE, "CIMx - Exiting commonInitEarlyBoot\n"));
}
/**
@@ -790,7 +790,7 @@ abcfgTbl (
UINT32 ddValue;
while ( (pABTbl->regType) != 0xFF ) {
- TRACE ((DMSG_SB_TRACE, "RegType: %X, RegNumber: %X, AndMask = %X, OrMask = %X \n", pABTbl->regType, pABTbl->regIndex, pABTbl->regMask, pABTbl->regData));
+ TRACE ((DMSG_SB_TRACE, "RegType: %X, RegNumber: %X, AndMask = %X, OrMask = %X\n", pABTbl->regType, pABTbl->regIndex, pABTbl->regMask, pABTbl->regData));
if ( pABTbl->regType == AXINDC ) {
ddValue = 0x30 | (pABTbl->regType << 29);
writeAlink (ddValue, (pABTbl->regIndex & 0x00FFFFFF));
diff --git a/src/vendorcode/amd/cimx/sb900/SbMain.c b/src/vendorcode/amd/cimx/sb900/SbMain.c
index 958e44b..c75564a 100644
--- a/src/vendorcode/amd/cimx/sb900/SbMain.c
+++ b/src/vendorcode/amd/cimx/sb900/SbMain.c
@@ -61,7 +61,7 @@ sbBeforePciInit (
IN AMDSBCFG* pConfig
)
{
- TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciInit \n"));
+ TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciInit\n"));
RecordSbConfigPtr ( (UINT32) ((UINTN) (pConfig)));
CheckEfuse (pConfig);
ValidateFchVariant (pConfig);
@@ -78,7 +78,7 @@ sbBeforePciInit (
sbPcieGppEarlyInit (pConfig); // Gpp port init
abSpecialSetBeforePciEnum (pConfig);
hwmInit (pConfig);
- TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbBeforePciInit \n"));
+ TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbBeforePciInit\n"));
}
/**
@@ -94,7 +94,7 @@ sbAfterPciInit (
IN AMDSBCFG* pConfig
)
{
- TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciInit \n"));
+ TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciInit\n"));
imcEnableSurebootTimer (pConfig);
usbInitAfterPciInit (pConfig); // Init USB MMIO
@@ -102,7 +102,7 @@ sbAfterPciInit (
gecInitAfterPciEnum (pConfig);
azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio
hwmUpdateData (pConfig);
- TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbAfterPciInit \n"));
+ TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbAfterPciInit\n"));
}
/**
@@ -118,10 +118,10 @@ sbMidPostInit (
IN AMDSBCFG* pConfig
)
{
- TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbMidPostInit \n"));
+ TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbMidPostInit\n"));
imcEnableSurebootTimer (pConfig);
sataInitMidPost (pConfig);
- TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbMidPostInit \n"));
+ TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbMidPostInit\n"));
}
/*----------------------------------------------------------------------------------------*/
@@ -141,7 +141,7 @@ sbLatePost (
// UINT16 dwVar;
BUILDPARAM *pStaticOptions;
pStaticOptions = &(pConfig->BuildParameters);
- TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n"));
+ TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbLatePost\n"));
commonInitLateBoot (pConfig);
sataInitLatePost (pConfig);
gecInitLatePost (pConfig);
@@ -172,7 +172,7 @@ sbBeforePciRestoreInit (
IN AMDSBCFG* pConfig
)
{
- TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciRestoreInit \n"));
+ TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciRestoreInit\n"));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
pConfig->S3Resume = 1;
ValidateFchVariant (pConfig);
@@ -208,7 +208,7 @@ sbAfterPciRestoreInit (
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
pStaticOptions = &(pConfig->BuildParameters);
- TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit \n"));
+ TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit\n"));
commonInitLateBoot (pConfig);
sataInitAfterPciEnum (pConfig);
gecInitAfterPciEnum (pConfig);
diff --git a/src/vendorcode/amd/cimx/sb900/SbPor.c b/src/vendorcode/amd/cimx/sb900/SbPor.c
index 90e878e..e97818b 100644
--- a/src/vendorcode/amd/cimx/sb900/SbPor.c
+++ b/src/vendorcode/amd/cimx/sb900/SbPor.c
@@ -192,7 +192,7 @@ sbPowerOnInit (
cimSataInternal100Spread = SataInternal100SpreadDefault;
#endif
- TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n"));
+ TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit\n"));
// Hudson-2 Only Enabled (Mmio_mem_enablr) // Default value is correct
RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0);
diff --git a/src/vendorcode/amd/cimx/sb900/Smm.c b/src/vendorcode/amd/cimx/sb900/Smm.c
index 51a4ccc..302c656 100644
--- a/src/vendorcode/amd/cimx/sb900/Smm.c
+++ b/src/vendorcode/amd/cimx/sb900/Smm.c
@@ -63,9 +63,9 @@ sbSmmService (
AMDSBCFG* pTmp; //lx-dummy for /W4 build
pTmp = pConfig;
- TRACE ((DMSG_SB_TRACE, "CIMx - Entering SMM services \n"));
+ TRACE ((DMSG_SB_TRACE, "CIMx - Entering SMM services\n"));
- TRACE ((DMSG_SB_TRACE, "CIMx - Exiting SMM services \n"));
+ TRACE ((DMSG_SB_TRACE, "CIMx - Exiting SMM services\n"));
}
/**
@@ -79,7 +79,7 @@ softwareSMIservice (
IN VOID
)
{
- TRACE ((DMSG_SB_TRACE, "SMI CMD Port Address: %X SMICMD Port value is %X \n", dwSmiCmdPort, dwVar));
+ TRACE ((DMSG_SB_TRACE, "SMI CMD Port Address: %X SMICMD Port value is %X\n", dwSmiCmdPort, dwVar));
}
diff --git a/src/vendorcode/amd/cimx/sb900/Usb.c b/src/vendorcode/amd/cimx/sb900/Usb.c
index 2d635ec..278173d 100644
--- a/src/vendorcode/amd/cimx/sb900/Usb.c
+++ b/src/vendorcode/amd/cimx/sb900/Usb.c
@@ -95,7 +95,7 @@ usbInitBeforePciEnum (
UINT8 XhciEfuse;
// add Efuse checking for Xhci enable/disable
XhciEfuse = XHCI_EFUSE_LOCATION;
- TRACE ((DMSG_SB_TRACE, "Entering PreInit Usb \n"));
+ TRACE ((DMSG_SB_TRACE, "Entering PreInit Usb\n"));
// Disabled All USB controller
// RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, BIT7, 0);
// Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST.
diff --git a/util/abuild/abuild b/util/abuild/abuild
index cbfc9dc..6326257 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -388,7 +388,7 @@ function myhelp
printf " [-p|--payloads <dir>] use payloads in <dir> to build images\n"
printf " [-V|--version] print version number and exit\n"
printf " [-h|--help] print this help and exit\n"
- printf " [-J|--junit] write JUnit formatted xml log file \n"
+ printf " [-J|--junit] write JUnit formatted xml log file\n"
printf " (defaults to $XMLFILE)\n"
printf " [-T|--test] submit image(s) to automated test system\n"
printf " [-c|--cpus <numcpus>] build on <numcpus> at the same time\n"
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 5aa98d5..6888a8f 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -264,7 +264,7 @@ fi
USE_GOLD=""
GCC_OPTIONS="--enable-lto"
-printf "Downloading tar balls ... \n"
+printf "Downloading tar balls ...\n"
mkdir -p tarballs
for ARCHIVE in $GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE $LIBELF_ARCHIVE \
$GCC_ARCHIVE $BINUTILS_ARCHIVE $GDB_ARCHIVE \
@@ -284,7 +284,7 @@ done
printf "Downloaded tar balls ... "
printf "${green}ok${NC}\n"
-printf "Unpacking and patching ... \n"
+printf "Unpacking and patching ...\n"
for PACKAGE in GMP MPFR MPC LIBELF GCC BINUTILS $PYTHON_PACKAGE \
$EXPAT_PACKAGE $GDB_PACKAGE IASL; do
archive=$PACKAGE"_ARCHIVE"
diff --git a/util/kconfig/gconf.c b/util/kconfig/gconf.c
index f2bee70..6500d99 100644
--- a/util/kconfig/gconf.c
+++ b/util/kconfig/gconf.c
@@ -677,7 +677,7 @@ void on_introduction1_activate(GtkMenuItem * menuitem, gpointer user_data)
"are interested in, you can still view the help of a grayed-out\n"
"option.\n"
"\n"
- "Toggling Show Debug Info under the Options menu will show \n"
+ "Toggling Show Debug Info under the Options menu will show\n"
"the dependencies, which you can then match by examining other options.");
dialog = gtk_message_dialog_new(GTK_WINDOW(main_wnd),
diff --git a/util/kconfig/nconf.c b/util/kconfig/nconf.c
index 4fbecd2..b14e59c 100644
--- a/util/kconfig/nconf.c
+++ b/util/kconfig/nconf.c
@@ -16,7 +16,7 @@
static const char nconf_global_help[] = N_(
"Help windows\n"
"------------\n"
-"o Global help: Unless in a data entry window, pressing <F1> will give \n"
+"o Global help: Unless in a data entry window, pressing <F1> will give\n"
" you the global help window, which you are just reading.\n"
"\n"
"o A short version of the global help is available by pressing <F3>.\n"
diff --git a/util/mkelfImage/linux-ia64/convert_params.c b/util/mkelfImage/linux-ia64/convert_params.c
index a58f4ad..bcba22c 100644
--- a/util/mkelfImage/linux-ia64/convert_params.c
+++ b/util/mkelfImage/linux-ia64/convert_params.c
@@ -244,7 +244,7 @@ static void convert_bhdr_params(Elf_Bhdr *bhdr)
if (next > end)
break;
#if 0
- printf("n_type: %x n_name(%d): n_desc(%d): \n",
+ printf("n_type: %x n_name(%d): n_desc(%d):\n",
hdr->n_type, hdr->n_namesz, hdr->n_descsz);
#endif
diff --git a/util/mkelfImage/main/mkelfImage.c b/util/mkelfImage/main/mkelfImage.c
index 0dcc8c2..8cbb538 100644
--- a/util/mkelfImage/main/mkelfImage.c
+++ b/util/mkelfImage/main/mkelfImage.c
@@ -541,7 +541,7 @@ void usage(void)
" --output=<filename> Output to <filename>\n"
" -t, --type=TYPE Specify the new kernel is of <type>.\n"
"\n"
- "Supported kernel types: \n"
+ "Supported kernel types:\n"
);
for(i = 0; i < file_types; i++) {
printf("%s\n", file_type[i].name);
diff --git a/util/mptable/mptable.c b/util/mptable/mptable.c
index 5b8a59d..f9ab3f5 100644
--- a/util/mptable/mptable.c
+++ b/util/mptable/mptable.c
@@ -824,7 +824,7 @@ static void MPConfigTableHeader(uint32_t pap)
}
/* process all the I/O Ints */
- printf("\t/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ \n");
+ printf("\t/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/\n");
for (c = count; c; c--) {
if (readType() == 3)
intEntry();
diff --git a/util/msrtool/sys.c b/util/msrtool/sys.c
index 82c2dbf..c490153 100644
--- a/util/msrtool/sys.c
+++ b/util/msrtool/sys.c
@@ -31,9 +31,9 @@ struct cpuid_t *cpuid(void) {
/* First, we need determine which vendor we have */
#if defined(__DARWIN__) && !defined(__LP64__)
asm volatile (
- "pushl %%ebx \n"
- "cpuid \n"
- "popl %%ebx \n"
+ "pushl %%ebx\n"
+ "cpuid\n"
+ "popl %%ebx\n"
: "=b" (outebx) : "a" (0) : "%ecx", "%edx"
);
#else
@@ -45,9 +45,9 @@ struct cpuid_t *cpuid(void) {
/* Then, identificate CPU itself */
#if defined(__DARWIN__) && !defined(__LP64__)
asm volatile (
- "pushl %%ebx \n"
- "cpuid \n"
- "popl %%ebx \n"
+ "pushl %%ebx\n"
+ "cpuid\n"
+ "popl %%ebx\n"
: "=a" (outeax) : "a" (1) : "%ecx", "%edx"
);
#else
diff --git a/util/optionlist/kconfig2wiki b/util/optionlist/kconfig2wiki
index b73afa5..b78f668 100755
--- a/util/optionlist/kconfig2wiki
+++ b/util/optionlist/kconfig2wiki
@@ -77,7 +77,7 @@ def readfile(filename):
description = htmlescape(zapquotes(words[1]))
elif words[0] in ("help", "---help---"):
sys.stdout.write("|- bgcolor=\"#eeeeee\"\n")
- sys.stdout.write("| %s || %s || %s || %s || \n" % (config,source,configtype,description) )
+ sys.stdout.write("| %s || %s || %s || %s ||\n" % (config,source,configtype,description) )
helplen = len(i[:i.find(words[0])].expandtabs())
elif words[0] == "comment":
sys.stdout.write("|- bgcolor=\"#eeeeee\"\n")
diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c
index 84270bb..31d5017 100644
--- a/util/romcc/romcc.c
+++ b/util/romcc/romcc.c
@@ -9192,7 +9192,7 @@ static void decompose_compound_types(struct compile_state *state)
}
#if DEBUG_DECOMPOSE_HIRES
- fprintf(fp, "decompose next: %p \n", next);
+ fprintf(fp, "decompose next: %p\n", next);
fflush(fp);
fprintf(fp, "next->op: %d %s\n",
next->op, tops(next->op));
@@ -14277,7 +14277,7 @@ static void compute_closure_variables(struct compile_state *state,
#if DEBUG_EXPLICIT_CLOSURES
/* Print out the variables to be enclosed */
loc(state->dbgout, state, fcall);
- fprintf(state->dbgout, "Alive: \n");
+ fprintf(state->dbgout, "Alive:\n");
for(set = *enclose; set; set = set->next) {
display_triple(state->dbgout, set->member);
}
@@ -25050,7 +25050,7 @@ static void usage(void)
fprintf(fp,
"\nUsage: romcc [options] <source>.c\n"
"Compile a C source file generating a binary that does not implicilty use RAM\n"
- "Options: \n"
+ "Options:\n"
"-o <output file name>\n"
"-f<option> Specify a generic compiler option\n"
"-m<option> Specify a arch dependent option\n"
diff --git a/util/vgabios/testbios.c b/util/vgabios/testbios.c
index c12e721..baa3010 100644
--- a/util/vgabios/testbios.c
+++ b/util/vgabios/testbios.c
@@ -118,7 +118,7 @@ X86EMU_pioFuncs myfuncs = {
void usage(char *name)
{
printf
- ("Usage: %s [-c codesegment] [-s size] [-b base] [-i ip] [-t] <filename> ... \n",
+ ("Usage: %s [-c codesegment] [-s size] [-b base] [-i ip] [-t] <filename> ...\n",
name);
}
@@ -209,7 +209,7 @@ int main(int argc, char **argv)
debugflag = strtol(optarg, 0, 0);
break;
default:
- printf("Unknown option \n");
+ printf("Unknown option\n");
usage(argv[0]);
return 1;
}
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