[coreboot-gerrit] New patch to review for coreboot: 1f183e0 northbridge/intel: Remove a trailing whitespace
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Tue Jul 22 18:25:38 CEST 2014
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6314
-gerrit
commit 1f183e0055ad7aa19de5b1fca2440ec3ed85b42e
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Tue Jul 22 18:25:28 2014 +0200
northbridge/intel: Remove a trailing whitespace
Change-Id: Ic8d6007898a08ade9d6e5947cd368b7a0545928a
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/northbridge/intel/e7520/e7520.h | 20 +--
src/northbridge/intel/e7525/e7525.h | 20 +--
.../intel/fsp_sandybridge/northbridge.h | 22 +--
src/northbridge/intel/haswell/haswell.h | 26 ++--
src/northbridge/intel/i3100/ep80579.h | 12 +-
src/northbridge/intel/i3100/i3100.h | 20 +--
src/northbridge/intel/i82830/smihandler.c | 10 +-
src/northbridge/intel/i945/i945.h | 8 +-
src/northbridge/intel/nehalem/nehalem.h | 22 +--
src/northbridge/intel/sandybridge/sandybridge.h | 22 +--
src/northbridge/intel/sch/raminit.h | 148 ++++++++++-----------
11 files changed, 165 insertions(+), 165 deletions(-)
diff --git a/src/northbridge/intel/e7520/e7520.h b/src/northbridge/intel/e7520/e7520.h
index 61401e4..18bef2d 100644
--- a/src/northbridge/intel/e7520/e7520.h
+++ b/src/northbridge/intel/e7520/e7520.h
@@ -15,14 +15,14 @@
#define CKEDIS 0X8D
#define DDRCSR 0X9A
#define DEVPRES 0X9C
-#define DEVPRES_D0F0 (1 << 0)
-#define DEVPRES_D1F0 (1 << 1)
-#define DEVPRES_D2F0 (1 << 2)
-#define DEVPRES_D3F0 (1 << 3)
-#define DEVPRES_D4F0 (1 << 4)
-#define DEVPRES_D5F0 (1 << 5)
-#define DEVPRES_D6F0 (1 << 6)
-#define DEVPRES_D7F0 (1 << 7)
+#define DEVPRES_D0F0 (1 << 0)
+#define DEVPRES_D1F0 (1 << 1)
+#define DEVPRES_D2F0 (1 << 2)
+#define DEVPRES_D3F0 (1 << 3)
+#define DEVPRES_D4F0 (1 << 4)
+#define DEVPRES_D5F0 (1 << 5)
+#define DEVPRES_D6F0 (1 << 6)
+#define DEVPRES_D7F0 (1 << 7)
#define ESMRC 0X9D
#define SMRC 0X9E
#define EXSMRC 0X9F
@@ -34,6 +34,6 @@
#define TOM 0XCC
#define EXPECBASE 0XCE
#define DEVPRES1 0XF4
-#define DEVPRES1_D0F1 (1 << 5)
-#define DEVPRES1_D8F0 (1 << 1)
+#define DEVPRES1_D0F1 (1 << 5)
+#define DEVPRES1_D8F0 (1 << 1)
#define MSCFG 0XF6
diff --git a/src/northbridge/intel/e7525/e7525.h b/src/northbridge/intel/e7525/e7525.h
index 61401e4..18bef2d 100644
--- a/src/northbridge/intel/e7525/e7525.h
+++ b/src/northbridge/intel/e7525/e7525.h
@@ -15,14 +15,14 @@
#define CKEDIS 0X8D
#define DDRCSR 0X9A
#define DEVPRES 0X9C
-#define DEVPRES_D0F0 (1 << 0)
-#define DEVPRES_D1F0 (1 << 1)
-#define DEVPRES_D2F0 (1 << 2)
-#define DEVPRES_D3F0 (1 << 3)
-#define DEVPRES_D4F0 (1 << 4)
-#define DEVPRES_D5F0 (1 << 5)
-#define DEVPRES_D6F0 (1 << 6)
-#define DEVPRES_D7F0 (1 << 7)
+#define DEVPRES_D0F0 (1 << 0)
+#define DEVPRES_D1F0 (1 << 1)
+#define DEVPRES_D2F0 (1 << 2)
+#define DEVPRES_D3F0 (1 << 3)
+#define DEVPRES_D4F0 (1 << 4)
+#define DEVPRES_D5F0 (1 << 5)
+#define DEVPRES_D6F0 (1 << 6)
+#define DEVPRES_D7F0 (1 << 7)
#define ESMRC 0X9D
#define SMRC 0X9E
#define EXSMRC 0X9F
@@ -34,6 +34,6 @@
#define TOM 0XCC
#define EXPECBASE 0XCE
#define DEVPRES1 0XF4
-#define DEVPRES1_D0F1 (1 << 5)
-#define DEVPRES1_D8F0 (1 << 1)
+#define DEVPRES1_D0F1 (1 << 5)
+#define DEVPRES1_D8F0 (1 << 1)
#define MSCFG 0XF6
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h
index 9a0cf42..e0eadff 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.h
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h
@@ -72,12 +72,12 @@
#define GGC 0x50 /* GMCH Graphics Control */
#define DEVEN 0x54 /* Device Enable */
-#define DEVEN_PEG60 (1 << 13)
-#define DEVEN_IGD (1 << 4)
-#define DEVEN_PEG10 (1 << 3)
-#define DEVEN_PEG11 (1 << 2)
-#define DEVEN_PEG12 (1 << 1)
-#define DEVEN_HOST (1 << 0)
+#define DEVEN_PEG60 (1 << 13)
+#define DEVEN_IGD (1 << 4)
+#define DEVEN_PEG10 (1 << 3)
+#define DEVEN_PEG11 (1 << 2)
+#define DEVEN_PEG12 (1 << 1)
+#define DEVEN_HOST (1 << 0)
#define PAM0 0x80
#define PAM1 0x81
@@ -89,11 +89,11 @@
#define LAC 0x87 /* Legacy Access Control */
#define SMRAM 0x88 /* System Management RAM Control */
-#define D_OPEN (1 << 6)
-#define D_CLS (1 << 5)
-#define D_LCK (1 << 4)
-#define G_SMRAME (1 << 3)
-#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
+#define D_OPEN (1 << 6)
+#define D_CLS (1 << 5)
+#define D_LCK (1 << 4)
+#define G_SMRAME (1 << 3)
+#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
#define TOM 0xa0
#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index bcd22d1..f491098 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -50,14 +50,14 @@
#define GGC 0x50 /* GMCH Graphics Control */
#define DEVEN 0x54 /* Device Enable */
-#define DEVEN_D7EN (1 << 14)
-#define DEVEN_D4EN (1 << 7)
-#define DEVEN_D3EN (1 << 5)
-#define DEVEN_D2EN (1 << 4)
-#define DEVEN_D1F0EN (1 << 3)
-#define DEVEN_D1F1EN (1 << 2)
-#define DEVEN_D1F2EN (1 << 1)
-#define DEVEN_D0EN (1 << 0)
+#define DEVEN_D7EN (1 << 14)
+#define DEVEN_D4EN (1 << 7)
+#define DEVEN_D3EN (1 << 5)
+#define DEVEN_D2EN (1 << 4)
+#define DEVEN_D1F0EN (1 << 3)
+#define DEVEN_D1F1EN (1 << 2)
+#define DEVEN_D1F2EN (1 << 1)
+#define DEVEN_D0EN (1 << 0)
#define PAM0 0x80
#define PAM1 0x81
@@ -69,11 +69,11 @@
#define LAC 0x87 /* Legacy Access Control */
#define SMRAM 0x88 /* System Management RAM Control */
-#define D_OPEN (1 << 6)
-#define D_CLS (1 << 5)
-#define D_LCK (1 << 4)
-#define G_SMRAME (1 << 3)
-#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
+#define D_OPEN (1 << 6)
+#define D_CLS (1 << 5)
+#define D_LCK (1 << 4)
+#define G_SMRAME (1 << 3)
+#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
#define MESEG_BASE 0x70 /* Management Engine Base. */
#define MESEG_LIMIT 0x78 /* Management Engine Limit. */
diff --git a/src/northbridge/intel/i3100/ep80579.h b/src/northbridge/intel/i3100/ep80579.h
index e9dee4d..c60e2a6 100644
--- a/src/northbridge/intel/i3100/ep80579.h
+++ b/src/northbridge/intel/i3100/ep80579.h
@@ -34,12 +34,12 @@
#define CKDIS 0x8c
#define CKEDIS 0x8d
#define DEVPRES 0x9c
-#define DEVPRES_D0F0 (1 << 0)
-#define DEVPRES_D1F0 (1 << 1)
-#define DEVPRES_D2F0 (1 << 2)
-#define DEVPRES_D3F0 (1 << 3)
-#define DEVPRES_D4F0 (1 << 4)
-#define DEVPRES_D10F0 (1 << 5)
+#define DEVPRES_D0F0 (1 << 0)
+#define DEVPRES_D1F0 (1 << 1)
+#define DEVPRES_D2F0 (1 << 2)
+#define DEVPRES_D3F0 (1 << 3)
+#define DEVPRES_D4F0 (1 << 4)
+#define DEVPRES_D10F0 (1 << 5)
#define EXSMRC 0x9d
#define SMRAM 0x9e
#define EXSMRAMC 0x9f
diff --git a/src/northbridge/intel/i3100/i3100.h b/src/northbridge/intel/i3100/i3100.h
index 2d036bd..eb0fedb 100644
--- a/src/northbridge/intel/i3100/i3100.h
+++ b/src/northbridge/intel/i3100/i3100.h
@@ -37,14 +37,14 @@
#define CKEDIS 0X8D
#define DDRCSR 0X9A
#define DEVPRES 0X9C
-#define DEVPRES_D0F0 (1 << 0)
-#define DEVPRES_D1F0 (1 << 1)
-#define DEVPRES_D2F0 (1 << 2)
-#define DEVPRES_D3F0 (1 << 3)
-#define DEVPRES_D4F0 (1 << 4)
-#define DEVPRES_D5F0 (1 << 5)
-#define DEVPRES_D6F0 (1 << 6)
-#define DEVPRES_D7F0 (1 << 7)
+#define DEVPRES_D0F0 (1 << 0)
+#define DEVPRES_D1F0 (1 << 1)
+#define DEVPRES_D2F0 (1 << 2)
+#define DEVPRES_D3F0 (1 << 3)
+#define DEVPRES_D4F0 (1 << 4)
+#define DEVPRES_D5F0 (1 << 5)
+#define DEVPRES_D6F0 (1 << 6)
+#define DEVPRES_D7F0 (1 << 7)
#define ESMRC 0X9D
#define SMRC 0X9E
#define EXSMRC 0X9F
@@ -56,8 +56,8 @@
#define TOM 0XCC
#define EXPECBASE 0XCE
#define DEVPRES1 0XF4
-#define DEVPRES1_D0F1 (1 << 5)
-#define DEVPRES1_D8F0 (1 << 1)
+#define DEVPRES1_D0F1 (1 << 5)
+#define DEVPRES1_D8F0 (1 << 1)
#define MSCFG 0XF6
/* DRC */
diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c
index e4d93cf..0a42406 100644
--- a/src/northbridge/intel/i82830/smihandler.c
+++ b/src/northbridge/intel/i82830/smihandler.c
@@ -44,11 +44,11 @@ extern u32 mbi_len;
/* I830M */
#define SMRAM 0x90
-#define D_OPEN (1 << 6)
-#define D_CLS (1 << 5)
-#define D_LCK (1 << 4)
-#define G_SMRANE (1 << 3)
-#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
+#define D_OPEN (1 << 6)
+#define D_CLS (1 << 5)
+#define D_LCK (1 << 4)
+#define G_SMRANE (1 << 3)
+#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
typedef struct {
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 9be9379..17e00f5 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -54,10 +54,10 @@
#define GGC 0x52 /* GMCH Graphics Control */
#define DEVEN 0x54 /* Device Enable */
-#define DEVEN_D0F0 (1 << 0)
-#define DEVEN_D1F0 (1 << 1)
-#define DEVEN_D2F0 (1 << 3)
-#define DEVEN_D2F1 (1 << 4)
+#define DEVEN_D0F0 (1 << 0)
+#define DEVEN_D1F0 (1 << 1)
+#define DEVEN_D2F0 (1 << 3)
+#define DEVEN_D2F1 (1 << 4)
#ifndef BOARD_DEVEN
#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 )
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index 60cafdf..3138dd7 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -205,12 +205,12 @@ enum {
#define D0F0_MCHBAR_HI 0x4c
#define D0F0_GGC 0x52
#define D0F0_DEVEN 0x54
-#define DEVEN_PEG60 (1 << 13)
-#define DEVEN_IGD (1 << 4)
-#define DEVEN_PEG10 (1 << 3)
-#define DEVEN_PEG11 (1 << 2)
-#define DEVEN_PEG12 (1 << 1)
-#define DEVEN_HOST (1 << 0)
+#define DEVEN_PEG60 (1 << 13)
+#define DEVEN_IGD (1 << 4)
+#define DEVEN_PEG10 (1 << 3)
+#define DEVEN_PEG11 (1 << 2)
+#define DEVEN_PEG12 (1 << 1)
+#define DEVEN_HOST (1 << 0)
#define D0F0_PCIEXBAR_LO 0x60
#define D0F0_PCIEXBAR_HI 0x64
#define D0F0_DMIBAR_LO 0x68
@@ -476,11 +476,11 @@ void init_iommu(void);
#define LAC 0x87 /* Legacy Access Control */
#define QPD0F1_SMRAM 0x4d /* System Management RAM Control */
-#define D_OPEN (1 << 6)
-#define D_CLS (1 << 5)
-#define D_LCK (1 << 4)
-#define G_SMRAME (1 << 3)
-#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
+#define D_OPEN (1 << 6)
+#define D_CLS (1 << 5)
+#define D_LCK (1 << 4)
+#define G_SMRAME (1 << 3)
+#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
#define SKPAD 0xdc /* Scratchpad Data */
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 291ea46..0a9c49c 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -69,12 +69,12 @@
#define GGC 0x50 /* GMCH Graphics Control */
#define DEVEN 0x54 /* Device Enable */
-#define DEVEN_PEG60 (1 << 13)
-#define DEVEN_IGD (1 << 4)
-#define DEVEN_PEG10 (1 << 3)
-#define DEVEN_PEG11 (1 << 2)
-#define DEVEN_PEG12 (1 << 1)
-#define DEVEN_HOST (1 << 0)
+#define DEVEN_PEG60 (1 << 13)
+#define DEVEN_IGD (1 << 4)
+#define DEVEN_PEG10 (1 << 3)
+#define DEVEN_PEG11 (1 << 2)
+#define DEVEN_PEG12 (1 << 1)
+#define DEVEN_HOST (1 << 0)
#define PAM0 0x80
#define PAM1 0x81
@@ -86,11 +86,11 @@
#define LAC 0x87 /* Legacy Access Control */
#define SMRAM 0x88 /* System Management RAM Control */
-#define D_OPEN (1 << 6)
-#define D_CLS (1 << 5)
-#define D_LCK (1 << 4)
-#define G_SMRAME (1 << 3)
-#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
+#define D_OPEN (1 << 6)
+#define D_CLS (1 << 5)
+#define D_LCK (1 << 4)
+#define G_SMRAME (1 << 3)
+#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
#define TOM 0xa0
#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
diff --git a/src/northbridge/intel/sch/raminit.h b/src/northbridge/intel/sch/raminit.h
index 179b87d..f139490 100644
--- a/src/northbridge/intel/sch/raminit.h
+++ b/src/northbridge/intel/sch/raminit.h
@@ -25,51 +25,51 @@
**/
#define BIT(x) (1<<x)
-#define EBP_TRP_MASK (BIT(1) | BIT(0))
-#define TRP_LOW 3h
-#define TRP_HIGH 5h
-#define EBP_TRP_OFFSET 0 /* Start of TRP field in EBP*/
-#define EBP_TRCD_MASK (BIT(3) | BIT(2))
-#define TRCD_LOW 3h
-#define TRCD_HIGH 5h
-#define EBP_TRCD_OFFSET 2 /* Start of TRCD field in EBP*/
-#define EBP_TCL_MASK (BIT(5) | BIT(4))
-#define TCL_LOW 3 /* Minimum supported CL*/
-#define TCL_HIGH 5 /* Maximum supported CL*/
-#define EBP_TCL_OFFSET 4 /* EBP bit( )for CL mask*/
-#define EBP_DDR2_CL_5_0 BIT(5) /* CL 5.0 = 10b*/
-#define EBP_DDR2_CL_4_0 BIT(4) /* CL 4.0 = 01b*/
-#define EBP_DDR2_CL_3_0 00h /* CL 3.0 = 00b*/
-#define EBP_FREQ_MASK (BIT(10)| BIT(9))
-#define EBP_FREQ_OFFSET 9 /* EBP bit( )for frequency mask*/
-#define EBP_FREQ_400 0 /* 400MHz EBP[10:9] = 00b*/
-#define EBP_FREQ_533 BIT(9) /* 533MHz EBP[10:9] = 01b*/
-#define EBP_REFRESH_MASK (BIT(12)| BIT(11))
-#define EBP_REFRESH_OFFSET 11 /* Bit offset of refresh field*/
-#define EBP_REF_DIS 00h /* Mask for refresh disabled*/
-#define EBP_REF_128CLK BIT(11) /* Mask for 128 clks referesh rate*/
-#define EBP_REF_3_9 BIT(12) /* Mask for 3.9us refresh rate*/
-#define EBP_REF_7_8 (BIT(12)| BIT(11))/* Mask for 7.8us refresh rate*/
-#define EBP_WIDTH_MASK BIT(15)
-#define EBP_WIDTH_OFFSET 15 /* Bit offset of EBP width field*/
-#define EBP_SOCKET_X16 BIT(15) /* Bit mask of x8/x16 bit*/
-#define EBP_DENSITY_MASK (BIT(17)| BIT(16))
-#define EBP_DENSITY_OFFSET 16
-#define EBP_DENSITY_512 BIT(16) /* 512Mbit density*/
-#define EBP_DENSITY_1024 BIT(17) /* 1024Mbit density*/
-#define EBP_DENSITY_2048 (BIT(17)| BIT(16))/* 2048Mbit density*/
-#define EBP_RANKS_MASK BIT(18)
-#define EBP_RANKS_OFFSET 18
-#define EBP_RANKS BIT(18) /* Bit offset of # of ranks bit*/
-#define EBP_PACKAGE_TYPE BIT(19) /* Package type (stacked or not)*/
-#define EBP_2X_MASK BIT(20)
-#define EBP_2X_OFFSET 20 /* Bit offset of ebp 2x refresh field*/
-#define EBP_2X_AUTO_REFRESH BIT(20) /* Bit mask of 2x refresh field*/
-#define EBP_DRAM_PARM_MASK BIT(21)
-#define EBP_DRAM_PARM_OFFSET 21
-#define EBP_DRAM_PARM_SPD 0 /* Use SPD to get DRAM parameters*/
-#define EBP_DRAM_PARM_CMC BIT(21) /* DRAM parameters in CMC binary*/
-#define EBP_BOOT_PATH BIT(31)
+#define EBP_TRP_MASK (BIT(1) | BIT(0))
+#define TRP_LOW 3h
+#define TRP_HIGH 5h
+#define EBP_TRP_OFFSET 0 /* Start of TRP field in EBP*/
+#define EBP_TRCD_MASK (BIT(3) | BIT(2))
+#define TRCD_LOW 3h
+#define TRCD_HIGH 5h
+#define EBP_TRCD_OFFSET 2 /* Start of TRCD field in EBP*/
+#define EBP_TCL_MASK (BIT(5) | BIT(4))
+#define TCL_LOW 3 /* Minimum supported CL*/
+#define TCL_HIGH 5 /* Maximum supported CL*/
+#define EBP_TCL_OFFSET 4 /* EBP bit( )for CL mask*/
+#define EBP_DDR2_CL_5_0 BIT(5) /* CL 5.0 = 10b*/
+#define EBP_DDR2_CL_4_0 BIT(4) /* CL 4.0 = 01b*/
+#define EBP_DDR2_CL_3_0 00h /* CL 3.0 = 00b*/
+#define EBP_FREQ_MASK (BIT(10)| BIT(9))
+#define EBP_FREQ_OFFSET 9 /* EBP bit( )for frequency mask*/
+#define EBP_FREQ_400 0 /* 400MHz EBP[10:9] = 00b*/
+#define EBP_FREQ_533 BIT(9) /* 533MHz EBP[10:9] = 01b*/
+#define EBP_REFRESH_MASK (BIT(12)| BIT(11))
+#define EBP_REFRESH_OFFSET 11 /* Bit offset of refresh field*/
+#define EBP_REF_DIS 00h /* Mask for refresh disabled*/
+#define EBP_REF_128CLK BIT(11) /* Mask for 128 clks referesh rate*/
+#define EBP_REF_3_9 BIT(12) /* Mask for 3.9us refresh rate*/
+#define EBP_REF_7_8 (BIT(12)| BIT(11))/* Mask for 7.8us refresh rate*/
+#define EBP_WIDTH_MASK BIT(15)
+#define EBP_WIDTH_OFFSET 15 /* Bit offset of EBP width field*/
+#define EBP_SOCKET_X16 BIT(15) /* Bit mask of x8/x16 bit*/
+#define EBP_DENSITY_MASK (BIT(17)| BIT(16))
+#define EBP_DENSITY_OFFSET 16
+#define EBP_DENSITY_512 BIT(16) /* 512Mbit density*/
+#define EBP_DENSITY_1024 BIT(17) /* 1024Mbit density*/
+#define EBP_DENSITY_2048 (BIT(17)| BIT(16))/* 2048Mbit density*/
+#define EBP_RANKS_MASK BIT(18)
+#define EBP_RANKS_OFFSET 18
+#define EBP_RANKS BIT(18) /* Bit offset of # of ranks bit*/
+#define EBP_PACKAGE_TYPE BIT(19) /* Package type (stacked or not)*/
+#define EBP_2X_MASK BIT(20)
+#define EBP_2X_OFFSET 20 /* Bit offset of ebp 2x refresh field*/
+#define EBP_2X_AUTO_REFRESH BIT(20) /* Bit mask of 2x refresh field*/
+#define EBP_DRAM_PARM_MASK BIT(21)
+#define EBP_DRAM_PARM_OFFSET 21
+#define EBP_DRAM_PARM_SPD 0 /* Use SPD to get DRAM parameters*/
+#define EBP_DRAM_PARM_CMC BIT(21) /* DRAM parameters in CMC binary*/
+#define EBP_BOOT_PATH BIT(31)
@@ -105,35 +105,35 @@
/* SCH Message Ports and Registers*/
-#define SCH_MSG_DUNIT_PORT 0x1 /* DRAM unit port */
-#define SCH_MSG_DUNIT_REG_DRP 0x0 /* DRAM Rank Population and Interface */
-#define DRP_FIELDS 0xFF /* Pertinent fields in DRP */
-#define DRP_RANK0_OFFSET 3 /* Rank 0 enable offset */
-#define DRP_RANK1_OFFSET 7 /* Rank 1 enable offset */
-#define DRP_DENSITY0_OFFSET 1 /* Density offset - Rank 0 */
-#define DRP_DENSITY1_OFFSET 5 /* Density offset - Rank 1 */
-#define DRP_WIDTH0_OFFSET 0 /* Width offset - Rank 0 */
-#define DRP_WIDTH1_OFFSET 4 /* Width offset - Rank 1 */
-#define DRP_CKE_DIS (BIT(14)| BIT(13)) /* CKE disable bits for both ranks */
-#define DRP_CKE_DIS0 BIT(13) /* CKE disable bit - Rank 0 */
-#define DRP_CKE_DIS1 BIT(14) /* CKE disable bit - Rank 1 */
-#define DRP_SCK_DIS (BIT(11)| BIT(10)) /* SCK/SCKB disable bits */
-#define DRP_SCK_DIS1 BIT(11) /* SCK[1]/SCKB[1] disable */
-#define DRP_SCK_DIS0 BIT(10) /* SCK[0]/SCKB[0] disable */
-#define SCH_MSG_DUNIT_REG_DTR 0x01 /* DRAM Timing Register */
-#define DTR_FIELDS 0x3F /* Pertinent fields in DTR */
-#define DTR_TCL_OFFSET 4 /* CAS latency offset */
-#define DTR_TRCD_OFFSET 2 /* RAS CAS Delay Offset */
-#define DTR_TRP_OFFSET 0 /* RAS Precharge Delay Offset */
-#define SCH_MSG_DUNIT_REG_DCO 0x2 /* DRAM Control Register */
-#define DCO_FIELDS 0xF /* Pertinent fields in DCO */
-#define DCO_REFRESH_OFFSET 2 /* Refresh Rate Field Offset */
-#define DCO_FREQ_OFFSET 0 /* DRAM Frequency Field Offset */
-#define DCO_IC BIT(7) /* Initialization complete bit */
-#define SCH_MSG_PUNIT_PORT 04h /* Punit Port */
-#define SCH_MSG_PUNIT_REG_PCR 71h /* Punit Control Register */
-#define SCH_MSG_TEST_PORT 05h /* Test port */
-#define SCH_MSG_TEST_REG_MSR 03h /* Mode and Status Register */
+#define SCH_MSG_DUNIT_PORT 0x1 /* DRAM unit port */
+#define SCH_MSG_DUNIT_REG_DRP 0x0 /* DRAM Rank Population and Interface */
+#define DRP_FIELDS 0xFF /* Pertinent fields in DRP */
+#define DRP_RANK0_OFFSET 3 /* Rank 0 enable offset */
+#define DRP_RANK1_OFFSET 7 /* Rank 1 enable offset */
+#define DRP_DENSITY0_OFFSET 1 /* Density offset - Rank 0 */
+#define DRP_DENSITY1_OFFSET 5 /* Density offset - Rank 1 */
+#define DRP_WIDTH0_OFFSET 0 /* Width offset - Rank 0 */
+#define DRP_WIDTH1_OFFSET 4 /* Width offset - Rank 1 */
+#define DRP_CKE_DIS (BIT(14)| BIT(13)) /* CKE disable bits for both ranks */
+#define DRP_CKE_DIS0 BIT(13) /* CKE disable bit - Rank 0 */
+#define DRP_CKE_DIS1 BIT(14) /* CKE disable bit - Rank 1 */
+#define DRP_SCK_DIS (BIT(11)| BIT(10)) /* SCK/SCKB disable bits */
+#define DRP_SCK_DIS1 BIT(11) /* SCK[1]/SCKB[1] disable */
+#define DRP_SCK_DIS0 BIT(10) /* SCK[0]/SCKB[0] disable */
+#define SCH_MSG_DUNIT_REG_DTR 0x01 /* DRAM Timing Register */
+#define DTR_FIELDS 0x3F /* Pertinent fields in DTR */
+#define DTR_TCL_OFFSET 4 /* CAS latency offset */
+#define DTR_TRCD_OFFSET 2 /* RAS CAS Delay Offset */
+#define DTR_TRP_OFFSET 0 /* RAS Precharge Delay Offset */
+#define SCH_MSG_DUNIT_REG_DCO 0x2 /* DRAM Control Register */
+#define DCO_FIELDS 0xF /* Pertinent fields in DCO */
+#define DCO_REFRESH_OFFSET 2 /* Refresh Rate Field Offset */
+#define DCO_FREQ_OFFSET 0 /* DRAM Frequency Field Offset */
+#define DCO_IC BIT(7) /* Initialization complete bit */
+#define SCH_MSG_PUNIT_PORT 04h /* Punit Port */
+#define SCH_MSG_PUNIT_REG_PCR 71h /* Punit Control Register */
+#define SCH_MSG_TEST_PORT 05h /* Test port */
+#define SCH_MSG_TEST_REG_MSR 03h /* Mode and Status Register */
/* Jedec initialization mapping into the MDR address field for DRAM init messages*/
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