[coreboot-gerrit] New patch to review for coreboot: f86a60d northbridge/amd: Remove a trailing whitespace
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Tue Jul 22 18:30:22 CEST 2014
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6316
-gerrit
commit f86a60d9307affce9fa0265db6eceeefbb459a63
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Tue Jul 22 18:30:39 2014 +0200
northbridge/amd: Remove a trailing whitespace
Change-Id: Iccad59ebac1c47ee3fd16c0c1244b62184cfd1bf
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/northbridge/amd/agesa/family10/amdfam10.h | 60 +-
src/northbridge/amd/amdfam10/amdfam10.h | 1176 ++++++++++++-------------
src/northbridge/amd/amdht/AsPsDefs.h | 2 +-
src/northbridge/amd/amdk8/f.h | 546 ++++++------
src/northbridge/amd/amdk8/pre_f.h | 74 +-
src/northbridge/amd/amdmct/wrappers/mcti.h | 12 +-
6 files changed, 935 insertions(+), 935 deletions(-)
diff --git a/src/northbridge/amd/agesa/family10/amdfam10.h b/src/northbridge/amd/agesa/family10/amdfam10.h
index 0026803..e630169 100644
--- a/src/northbridge/amd/agesa/family10/amdfam10.h
+++ b/src/northbridge/amd/agesa/family10/amdfam10.h
@@ -36,36 +36,36 @@
/* Definitions of various FAM10 registers */
/* Function 0 */
#define HT_TRANSACTION_CONTROL 0x68
-#define HTTC_DIS_RD_B_P (1 << 0)
-#define HTTC_DIS_RD_DW_P (1 << 1)
-#define HTTC_DIS_WR_B_P (1 << 2)
-#define HTTC_DIS_WR_DW_P (1 << 3)
-#define HTTC_DIS_MTS (1 << 4)
-#define HTTC_CPU1_EN (1 << 5)
-#define HTTC_CPU_REQ_PASS_PW (1 << 6)
-#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
-#define HTTC_DIS_P_MEM_C (1 << 8)
-#define HTTC_DIS_RMT_MEM_C (1 << 9)
-#define HTTC_DIS_FILL_P (1 << 10)
-#define HTTC_RSP_PASS_PW (1 << 11)
-#define HTTC_BUF_REL_PRI_SHIFT 13
-#define HTTC_BUF_REL_PRI_MASK 3
-#define HTTC_BUF_REL_PRI_64 0
-#define HTTC_BUF_REL_PRI_16 1
-#define HTTC_BUF_REL_PRI_8 2
-#define HTTC_BUF_REL_PRI_2 3
-#define HTTC_LIMIT_CLDT_CFG (1 << 15)
-#define HTTC_LINT_EN (1 << 16)
-#define HTTC_APIC_EXT_BRD_CST (1 << 17)
-#define HTTC_APIC_EXT_ID (1 << 18)
-#define HTTC_APIC_EXT_SPUR (1 << 19)
-#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
-#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
-#define HTTC_DS_NP_REQ_LIMIT_MASK 3
-#define HTTC_DS_NP_REQ_LIMIT_NONE 0
-#define HTTC_DS_NP_REQ_LIMIT_1 1
-#define HTTC_DS_NP_REQ_LIMIT_4 2
-#define HTTC_DS_NP_REQ_LIMIT_8 3
+#define HTTC_DIS_RD_B_P (1 << 0)
+#define HTTC_DIS_RD_DW_P (1 << 1)
+#define HTTC_DIS_WR_B_P (1 << 2)
+#define HTTC_DIS_WR_DW_P (1 << 3)
+#define HTTC_DIS_MTS (1 << 4)
+#define HTTC_CPU1_EN (1 << 5)
+#define HTTC_CPU_REQ_PASS_PW (1 << 6)
+#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
+#define HTTC_DIS_P_MEM_C (1 << 8)
+#define HTTC_DIS_RMT_MEM_C (1 << 9)
+#define HTTC_DIS_FILL_P (1 << 10)
+#define HTTC_RSP_PASS_PW (1 << 11)
+#define HTTC_BUF_REL_PRI_SHIFT 13
+#define HTTC_BUF_REL_PRI_MASK 3
+#define HTTC_BUF_REL_PRI_64 0
+#define HTTC_BUF_REL_PRI_16 1
+#define HTTC_BUF_REL_PRI_8 2
+#define HTTC_BUF_REL_PRI_2 3
+#define HTTC_LIMIT_CLDT_CFG (1 << 15)
+#define HTTC_LINT_EN (1 << 16)
+#define HTTC_APIC_EXT_BRD_CST (1 << 17)
+#define HTTC_APIC_EXT_ID (1 << 18)
+#define HTTC_APIC_EXT_SPUR (1 << 19)
+#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
+#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
+#define HTTC_DS_NP_REQ_LIMIT_MASK 3
+#define HTTC_DS_NP_REQ_LIMIT_NONE 0
+#define HTTC_DS_NP_REQ_LIMIT_1 1
+#define HTTC_DS_NP_REQ_LIMIT_4 2
+#define HTTC_DS_NP_REQ_LIMIT_8 3
/* Function 1 */
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 6e71b4e..f49d2d5 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -23,36 +23,36 @@
/* Definitions of various FAM10 registers */
/* Function 0 */
#define HT_TRANSACTION_CONTROL 0x68
-#define HTTC_DIS_RD_B_P (1 << 0)
-#define HTTC_DIS_RD_DW_P (1 << 1)
-#define HTTC_DIS_WR_B_P (1 << 2)
-#define HTTC_DIS_WR_DW_P (1 << 3)
-#define HTTC_DIS_MTS (1 << 4)
-#define HTTC_CPU1_EN (1 << 5)
-#define HTTC_CPU_REQ_PASS_PW (1 << 6)
-#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
-#define HTTC_DIS_P_MEM_C (1 << 8)
-#define HTTC_DIS_RMT_MEM_C (1 << 9)
-#define HTTC_DIS_FILL_P (1 << 10)
-#define HTTC_RSP_PASS_PW (1 << 11)
-#define HTTC_BUF_REL_PRI_SHIFT 13
-#define HTTC_BUF_REL_PRI_MASK 3
-#define HTTC_BUF_REL_PRI_64 0
-#define HTTC_BUF_REL_PRI_16 1
-#define HTTC_BUF_REL_PRI_8 2
-#define HTTC_BUF_REL_PRI_2 3
-#define HTTC_LIMIT_CLDT_CFG (1 << 15)
-#define HTTC_LINT_EN (1 << 16)
-#define HTTC_APIC_EXT_BRD_CST (1 << 17)
-#define HTTC_APIC_EXT_ID (1 << 18)
-#define HTTC_APIC_EXT_SPUR (1 << 19)
-#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
-#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
-#define HTTC_DS_NP_REQ_LIMIT_MASK 3
-#define HTTC_DS_NP_REQ_LIMIT_NONE 0
-#define HTTC_DS_NP_REQ_LIMIT_1 1
-#define HTTC_DS_NP_REQ_LIMIT_4 2
-#define HTTC_DS_NP_REQ_LIMIT_8 3
+#define HTTC_DIS_RD_B_P (1 << 0)
+#define HTTC_DIS_RD_DW_P (1 << 1)
+#define HTTC_DIS_WR_B_P (1 << 2)
+#define HTTC_DIS_WR_DW_P (1 << 3)
+#define HTTC_DIS_MTS (1 << 4)
+#define HTTC_CPU1_EN (1 << 5)
+#define HTTC_CPU_REQ_PASS_PW (1 << 6)
+#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
+#define HTTC_DIS_P_MEM_C (1 << 8)
+#define HTTC_DIS_RMT_MEM_C (1 << 9)
+#define HTTC_DIS_FILL_P (1 << 10)
+#define HTTC_RSP_PASS_PW (1 << 11)
+#define HTTC_BUF_REL_PRI_SHIFT 13
+#define HTTC_BUF_REL_PRI_MASK 3
+#define HTTC_BUF_REL_PRI_64 0
+#define HTTC_BUF_REL_PRI_16 1
+#define HTTC_BUF_REL_PRI_8 2
+#define HTTC_BUF_REL_PRI_2 3
+#define HTTC_LIMIT_CLDT_CFG (1 << 15)
+#define HTTC_LINT_EN (1 << 16)
+#define HTTC_APIC_EXT_BRD_CST (1 << 17)
+#define HTTC_APIC_EXT_ID (1 << 18)
+#define HTTC_APIC_EXT_SPUR (1 << 19)
+#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
+#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
+#define HTTC_DS_NP_REQ_LIMIT_MASK 3
+#define HTTC_DS_NP_REQ_LIMIT_NONE 0
+#define HTTC_DS_NP_REQ_LIMIT_1 1
+#define HTTC_DS_NP_REQ_LIMIT_4 2
+#define HTTC_DS_NP_REQ_LIMIT_8 3
/* Function 1 */
@@ -70,58 +70,58 @@
#define DRAM_BANK_ADDR_MAP 0x80
#define DRAM_CTRL 0x78
-#define DC_RdPtrInit_SHIFT 0
-#define DC_RdPrtInit_MASK 0xf
-#define DC_Twrrd3_2_SHIFT 8 /*DDR3 */
-#define DC_Twrrd3_2_MASK 3
-#define DC_Twrwr3_2_SHIFT 10 /*DDR3 */
-#define DC_Twrwr3_2_MASK 3
-#define DC_Trdrd3_2_SHIFT 12 /*DDR3 */
-#define DC_Trdrd3_2_MASK 3
-#define DC_AltVidC3MemClkTriEn (1<<16)
-#define DC_DqsRcvEnTrain (1<<18)
-#define DC_MaxRdLatency_SHIFT 22
-#define DC_MaxRdLatency_MASK 0x3ff
+#define DC_RdPtrInit_SHIFT 0
+#define DC_RdPrtInit_MASK 0xf
+#define DC_Twrrd3_2_SHIFT 8 /*DDR3 */
+#define DC_Twrrd3_2_MASK 3
+#define DC_Twrwr3_2_SHIFT 10 /*DDR3 */
+#define DC_Twrwr3_2_MASK 3
+#define DC_Trdrd3_2_SHIFT 12 /*DDR3 */
+#define DC_Trdrd3_2_MASK 3
+#define DC_AltVidC3MemClkTriEn (1<<16)
+#define DC_DqsRcvEnTrain (1<<18)
+#define DC_MaxRdLatency_SHIFT 22
+#define DC_MaxRdLatency_MASK 0x3ff
#define DRAM_INIT 0x7c
-#define DI_MrsAddress_SHIFT 0
-#define DI_MrsAddress_MASK 0xffff
-#define DI_MrsBank_SHIFT 16
-#define DI_MrsBank_MASK 7
-#define DI_MrsChipSel_SHIFT 20
-#define DI_MrsChipSel_MASK 7
-#define DI_SendRchgAll (1<<24)
-#define DI_SendAutoRefresh (1<<25)
-#define DI_SendMrsCmd (1<<26)
-#define DI_DeassertMemRstX (1<<27)
-#define DI_AssertCke (1<<28)
-#define DI_SendZQCmd (1<<29) /*DDR3 */
-#define DI_EnMrsCmd (1<<30)
-#define DI_EnDramInit (1<<31)
+#define DI_MrsAddress_SHIFT 0
+#define DI_MrsAddress_MASK 0xffff
+#define DI_MrsBank_SHIFT 16
+#define DI_MrsBank_MASK 7
+#define DI_MrsChipSel_SHIFT 20
+#define DI_MrsChipSel_MASK 7
+#define DI_SendRchgAll (1<<24)
+#define DI_SendAutoRefresh (1<<25)
+#define DI_SendMrsCmd (1<<26)
+#define DI_DeassertMemRstX (1<<27)
+#define DI_AssertCke (1<<28)
+#define DI_SendZQCmd (1<<29) /*DDR3 */
+#define DI_EnMrsCmd (1<<30)
+#define DI_EnDramInit (1<<31)
#define DRAM_MRS 0x84
-#define DM_BurstCtrl_SHIFT 0
-#define DM_BurstCtrl_MASK 3
-#define DM_DrvImpCtrl_SHIFT 2 /* DDR3 */
-#define DM_DrvImpCtrl_MASK 3
-#define DM_Twr_SHIFT 4 /* DDR3 */
-#define DM_Twr_MASK 7
-#define DM_Twr_BASE 4
-#define DM_Twr_MIN 5
-#define DM_Twr_MAX 12
-#define DM_DramTerm_SHIFT 7 /*DDR3 */
-#define DM_DramTerm_MASK 7
-#define DM_DramTermDyn_SHIFT 10 /* DDR3 */
-#define DM_DramTermDyn_MASK 3
-#define DM_Ooff (1<<13)
-#define DM_ASR (1<<18)
-#define DM_SRT (1<<19)
-#define DM_Tcwl_SHIFT 20
-#define DM_Tcwl_MASK 7
-#define DM_PchgPDModeSel (1<<23) /* DDR3 */
-#define DM_MPrLoc_SHIFT 24 /* DDR3 */
-#define DM_MPrLoc_MASK 3
-#define DM_MprEn (1<<26) /* DDR3 */
+#define DM_BurstCtrl_SHIFT 0
+#define DM_BurstCtrl_MASK 3
+#define DM_DrvImpCtrl_SHIFT 2 /* DDR3 */
+#define DM_DrvImpCtrl_MASK 3
+#define DM_Twr_SHIFT 4 /* DDR3 */
+#define DM_Twr_MASK 7
+#define DM_Twr_BASE 4
+#define DM_Twr_MIN 5
+#define DM_Twr_MAX 12
+#define DM_DramTerm_SHIFT 7 /*DDR3 */
+#define DM_DramTerm_MASK 7
+#define DM_DramTermDyn_SHIFT 10 /* DDR3 */
+#define DM_DramTermDyn_MASK 3
+#define DM_Ooff (1<<13)
+#define DM_ASR (1<<18)
+#define DM_SRT (1<<19)
+#define DM_Tcwl_SHIFT 20
+#define DM_Tcwl_MASK 7
+#define DM_PchgPDModeSel (1<<23) /* DDR3 */
+#define DM_MPrLoc_SHIFT 24 /* DDR3 */
+#define DM_MPrLoc_MASK 3
+#define DM_MprEn (1<<26) /* DDR3 */
#define DRAM_TIMING_LOW 0x88
#define DTL_TCL_SHIFT 0
@@ -133,17 +133,17 @@
#define DTL_TRCD_MASK 3 /* DDR3 =7 */
#define DTL_TRCD_BASE 3 /* DDR3 =5 */
#define DTL_TRCD_MIN 3 /* DDR3 =5 */
-#define DTL_TRCD_MAX 6 /* DDR3 =12 */
+#define DTL_TRCD_MAX 6 /* DDR3 =12 */
#define DTL_TRP_SHIFT 8 /* DDR3 =7 */
#define DTL_TRP_MASK 3 /* DDR3 =7 */
#define DTL_TRP_BASE 3 /* DDR3 =5 */
#define DTL_TRP_MIN 3 /* DDR3 =5 */
-#define DTL_TRP_MAX 6 /* DDR3 =12 */
+#define DTL_TRP_MAX 6 /* DDR3 =12 */
#define DTL_TRTP_SHIFT 11 /*DDR3 =10 */
#define DTL_TRTP_MASK 1 /*DDR3 =3 */
#define DTL_TRTP_BASE 2 /* DDR3 =4 */
#define DTL_TRTP_MIN 2 /* 4 for 64 bytes*/ /* DDR3 =4 for 32bytes or 64bytes */
-#define DTL_TRTP_MAX 3 /* 5 for 64 bytes */ /* DDR3 =7 for 32Bytes or 64bytes */
+#define DTL_TRTP_MAX 3 /* 5 for 64 bytes */ /* DDR3 =7 for 32Bytes or 64bytes */
#define DTL_TRAS_SHIFT 12
#define DTL_TRAS_MASK 0xf
#define DTL_TRAS_BASE 3 /* DDR3 =15 */
@@ -159,29 +159,29 @@
#define DTL_TWR_BASE 3
#define DTL_TWR_MIN 3
#define DTL_TWR_MAX 6
-#define DTL_TRRD_SHIFT 22
-#define DTL_TRRD_MASK 3
-#define DTL_TRRD_BASE 2 /* DDR3 =4 */
-#define DTL_TRRD_MIN 2 /* DDR3 =4 */
-#define DTL_TRRD_MAX 5 /* DDR3 =7 */
-#define DTL_MemClkDis_SHIFT 24 /* Channel A */
-#define DTL_MemClkDis3 (1 << 26)
-#define DTL_MemClkDis2 (1 << 27)
-#define DTL_MemClkDis1 (1 << 28)
-#define DTL_MemClkDis0 (1 << 29)
+#define DTL_TRRD_SHIFT 22
+#define DTL_TRRD_MASK 3
+#define DTL_TRRD_BASE 2 /* DDR3 =4 */
+#define DTL_TRRD_MIN 2 /* DDR3 =4 */
+#define DTL_TRRD_MAX 5 /* DDR3 =7 */
+#define DTL_MemClkDis_SHIFT 24 /* Channel A */
+#define DTL_MemClkDis3 (1 << 26)
+#define DTL_MemClkDis2 (1 << 27)
+#define DTL_MemClkDis1 (1 << 28)
+#define DTL_MemClkDis0 (1 << 29)
/* DTL_MemClkDis for m2 and s1g1 is different */
#define DRAM_TIMING_HIGH 0x8c
-#define DTH_TRWTWB_SHIFT 0
-#define DTH_TRWTWB_MASK 3
-#define DTH_TRWTWB_BASE 3 /* DDR3 =4 */
-#define DTH_TRWTWB_MIN 3 /* DDR3 =5 */
-#define DTH_TRWTWB_MAX 10 /* DDR3 =11 */
-#define DTH_TRWTTO_SHIFT 4
-#define DTH_TRWTTO_MASK 7
-#define DTH_TRWTTO_BASE 2 /* DDR3 =3 */
-#define DTH_TRWTTO_MIN 2 /* DDR3 =3 */
-#define DTH_TRWTTO_MAX 9 /* DDR3 =10 */
+#define DTH_TRWTWB_SHIFT 0
+#define DTH_TRWTWB_MASK 3
+#define DTH_TRWTWB_BASE 3 /* DDR3 =4 */
+#define DTH_TRWTWB_MIN 3 /* DDR3 =5 */
+#define DTH_TRWTWB_MAX 10 /* DDR3 =11 */
+#define DTH_TRWTTO_SHIFT 4
+#define DTH_TRWTTO_MASK 7
+#define DTH_TRWTTO_BASE 2 /* DDR3 =3 */
+#define DTH_TRWTTO_MIN 2 /* DDR3 =3 */
+#define DTH_TRWTTO_MAX 9 /* DDR3 =10 */
#define DTH_TWTR_SHIFT 8
#define DTH_TWTR_MASK 3
#define DTH_TWTR_BASE 0 /* DDR3 =4 */
@@ -192,114 +192,114 @@
#define DTH_TWRRD_BASE 0 /* DDR3 =0 */
#define DTH_TWRRD_MIN 0 /* DDR3 =2 */
#define DTH_TWRRD_MAX 3 /* DDR3 =12 */
-#define DTH_TWRWR_SHIFT 12
-#define DTH_TWRWR_MASK 3 /* For DDR3 3_2 is at 0x78 DC */
-#define DTH_TWRWR_BASE 1
-#define DTH_TWRWR_MIN 1 /* DDR3 =3 */
-#define DTH_TWRWR_MAX 3 /* DDR3 =12 */
-#define DTH_TRDRD_SHIFT 14
-#define DTH_TRDRD_MASK 3 /* For DDR3 3_2 is at 0x78 DC */
-#define DTH_TRDRD_BASE 2
-#define DTH_TRDRD_MIN 2
-#define DTH_TRDRD_MAX 5 /* DDR3 =10 */
+#define DTH_TWRWR_SHIFT 12
+#define DTH_TWRWR_MASK 3 /* For DDR3 3_2 is at 0x78 DC */
+#define DTH_TWRWR_BASE 1
+#define DTH_TWRWR_MIN 1 /* DDR3 =3 */
+#define DTH_TWRWR_MAX 3 /* DDR3 =12 */
+#define DTH_TRDRD_SHIFT 14
+#define DTH_TRDRD_MASK 3 /* For DDR3 3_2 is at 0x78 DC */
+#define DTH_TRDRD_BASE 2
+#define DTH_TRDRD_MIN 2
+#define DTH_TRDRD_MAX 5 /* DDR3 =10 */
#define DTH_TREF_SHIFT 16
#define DTH_TREF_MASK 3
#define DTH_TREF_7_8_US 2
#define DTH_TREF_3_9_US 3
-#define DTH_DisAutoRefresh (1<<18)
-#define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */
-#define DTH_TRFC_MASK 7
+#define DTH_DisAutoRefresh (1<<18)
+#define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */
+#define DTH_TRFC_MASK 7
#define DTH_TRFC_75_256M 0
#define DTH_TRFC_105_512M 1
-#define DTH_TRFC_127_5_1G 2
-#define DTH_TRFC_195_2G 3
-#define DTH_TRFC_327_5_4G 4
+#define DTH_TRFC_127_5_1G 2
+#define DTH_TRFC_195_2G 3
+#define DTH_TRFC_327_5_4G 4
#if 0
//DDR3
-#define DTH_TRFC_90_512M 1
-#define DTH_TRFC_110_5_1G 2
-#define DTH_TRFC_160_2G 3
-#define DTH_TRFC_300_4G 4
-#define DTH_TRFC_UNDEFINED_8G 5
+#define DTH_TRFC_90_512M 1
+#define DTH_TRFC_110_5_1G 2
+#define DTH_TRFC_160_2G 3
+#define DTH_TRFC_300_4G 4
+#define DTH_TRFC_UNDEFINED_8G 5
#endif
-#define DTH_TRFC1_SHIFT 23 /*for Logical DIMM1 */
-#define DTH_TRFC2_SHIFT 26 /*for Logical DIMM2 */
-#define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */
+#define DTH_TRFC1_SHIFT 23 /*for Logical DIMM1 */
+#define DTH_TRFC2_SHIFT 26 /*for Logical DIMM2 */
+#define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */
#define DRAM_CONFIG_LOW 0x90
#define DCL_InitDram (1<<0)
#define DCL_ExitSelfRef (1<<1)
-#define DCL_PllLockTime_SHIFT 2
-#define DCL_PllLockTime_MASK 3
-#define DCL_PllLockTime_15US 0
-#define DCL_PllLockTime_6US 1
-#define DCL_DramTerm_SHIFT 4
-#define DCL_DramTerm_MASK 3
-#define DCL_DramTerm_No 0
-#define DCL_DramTerm_75_OH 1
-#define DCL_DramTerm_150_OH 2
-#define DCL_DramTerm_50_OH 3
-#define DCL_DisDqsBar (1<<6) /* only for DDR2 */
-#define DCL_DramDrvWeak (1<<7) /* only for DDR2 */
-#define DCL_ParEn (1<<8)
-#define DCL_SelfRefRateEn (1<<9) /* only for DDR2 */
-#define DCL_BurstLength32 (1<<10) /* only for DDR3 */
-#define DCL_Width128 (1<<11)
-#define DCL_X4Dimm_SHIFT 12
-#define DCL_X4Dimm_MASK 0xf
-#define DCL_UnBuffDimm (1<<16)
-#define DCL_EnPhyDqsRcvEnTr (1<<18)
+#define DCL_PllLockTime_SHIFT 2
+#define DCL_PllLockTime_MASK 3
+#define DCL_PllLockTime_15US 0
+#define DCL_PllLockTime_6US 1
+#define DCL_DramTerm_SHIFT 4
+#define DCL_DramTerm_MASK 3
+#define DCL_DramTerm_No 0
+#define DCL_DramTerm_75_OH 1
+#define DCL_DramTerm_150_OH 2
+#define DCL_DramTerm_50_OH 3
+#define DCL_DisDqsBar (1<<6) /* only for DDR2 */
+#define DCL_DramDrvWeak (1<<7) /* only for DDR2 */
+#define DCL_ParEn (1<<8)
+#define DCL_SelfRefRateEn (1<<9) /* only for DDR2 */
+#define DCL_BurstLength32 (1<<10) /* only for DDR3 */
+#define DCL_Width128 (1<<11)
+#define DCL_X4Dimm_SHIFT 12
+#define DCL_X4Dimm_MASK 0xf
+#define DCL_UnBuffDimm (1<<16)
+#define DCL_EnPhyDqsRcvEnTr (1<<18)
#define DCL_DimmEccEn (1<<19)
-#define DCL_DynPageCloseEn (1<<20)
-#define DCL_IdleCycInit_SHIFT 21
-#define DCL_IdleCycInit_MASK 3
-#define DCL_IdleCycInit_16CLK 0
-#define DCL_IdleCycInit_32CLK 1
-#define DCL_IdleCycInit_64CLK 2
-#define DCL_IdleCycInit_96CLK 3
-#define DCL_ForceAutoPchg (1<<23)
+#define DCL_DynPageCloseEn (1<<20)
+#define DCL_IdleCycInit_SHIFT 21
+#define DCL_IdleCycInit_MASK 3
+#define DCL_IdleCycInit_16CLK 0
+#define DCL_IdleCycInit_32CLK 1
+#define DCL_IdleCycInit_64CLK 2
+#define DCL_IdleCycInit_96CLK 3
+#define DCL_ForceAutoPchg (1<<23)
#define DRAM_CONFIG_HIGH 0x94
-#define DCH_MemClkFreq_SHIFT 0
-#define DCH_MemClkFreq_MASK 7
-#define DCH_MemClkFreq_200MHz 0 /* DDR2 */
-#define DCH_MemClkFreq_266MHz 1 /* DDR2 */
-#define DCH_MemClkFreq_333MHz 2 /* DDR2 */
+#define DCH_MemClkFreq_SHIFT 0
+#define DCH_MemClkFreq_MASK 7
+#define DCH_MemClkFreq_200MHz 0 /* DDR2 */
+#define DCH_MemClkFreq_266MHz 1 /* DDR2 */
+#define DCH_MemClkFreq_333MHz 2 /* DDR2 */
#define DCH_MemClkFreq_400MHz 3 /* DDR2 and DDR 3*/
#define DCH_MemClkFreq_533MHz 4 /* DDR 3 */
#define DCH_MemClkFreq_667MHz 5 /* DDR 3 */
#define DCH_MemClkFreq_800MHz 6 /* DDR 3 */
-#define DCH_MemClkFreqVal (1<<3)
-#define DCH_Ddr3Mode (1<<8)
-#define DCH_LegacyBiosMode (1<<9)
-#define DCH_ZqcsInterval_SHIFT 10
-#define DCH_ZqcsInterval_MASK 3
-#define DCH_ZqcsInterval_DIS 0
-#define DCH_ZqcsInterval_64MS 1
-#define DCH_ZqcsInterval_128MS 2
-#define DCH_ZqcsInterval_256MS 3
-#define DCH_RDqsEn (1<<12) /* only for DDR2 */
-#define DCH_DisSimulRdWr (1<<13)
-#define DCH_DisDramInterface (1<<14)
-#define DCH_PowerDownEn (1<<15)
-#define DCH_PowerDownMode_SHIFT 16
-#define DCH_PowerDownMode_MASK 1
-#define DCH_PowerDownMode_Channel_CKE 0
-#define DCH_PowerDownMode_ChipSelect_CKE 1
-#define DCH_FourRankSODimm (1<<17)
-#define DCH_FourRankRDimm (1<<18)
-#define DCH_SlowAccessMode (1<<20)
-#define DCH_BankSwizzleMode (1<<22)
-#define DCH_DcqBypassMax_SHIFT 24
-#define DCH_DcqBypassMax_MASK 0xf
-#define DCH_DcqBypassMax_BASE 0
-#define DCH_DcqBypassMax_MIN 0
-#define DCH_DcqBypassMax_MAX 15
-#define DCH_FourActWindow_SHIFT 28
-#define DCH_FourActWindow_MASK 0xf
-#define DCH_FourActWindow_BASE 7 /* DDR3 15 */
-#define DCH_FourActWindow_MIN 8 /* DDR3 16 */
-#define DCH_FourActWindow_MAX 20 /* DDR3 30 */
+#define DCH_MemClkFreqVal (1<<3)
+#define DCH_Ddr3Mode (1<<8)
+#define DCH_LegacyBiosMode (1<<9)
+#define DCH_ZqcsInterval_SHIFT 10
+#define DCH_ZqcsInterval_MASK 3
+#define DCH_ZqcsInterval_DIS 0
+#define DCH_ZqcsInterval_64MS 1
+#define DCH_ZqcsInterval_128MS 2
+#define DCH_ZqcsInterval_256MS 3
+#define DCH_RDqsEn (1<<12) /* only for DDR2 */
+#define DCH_DisSimulRdWr (1<<13)
+#define DCH_DisDramInterface (1<<14)
+#define DCH_PowerDownEn (1<<15)
+#define DCH_PowerDownMode_SHIFT 16
+#define DCH_PowerDownMode_MASK 1
+#define DCH_PowerDownMode_Channel_CKE 0
+#define DCH_PowerDownMode_ChipSelect_CKE 1
+#define DCH_FourRankSODimm (1<<17)
+#define DCH_FourRankRDimm (1<<18)
+#define DCH_SlowAccessMode (1<<20)
+#define DCH_BankSwizzleMode (1<<22)
+#define DCH_DcqBypassMax_SHIFT 24
+#define DCH_DcqBypassMax_MASK 0xf
+#define DCH_DcqBypassMax_BASE 0
+#define DCH_DcqBypassMax_MIN 0
+#define DCH_DcqBypassMax_MAX 15
+#define DCH_FourActWindow_SHIFT 28
+#define DCH_FourActWindow_MASK 0xf
+#define DCH_FourActWindow_BASE 7 /* DDR3 15 */
+#define DCH_FourActWindow_MIN 8 /* DDR3 16 */
+#define DCH_FourActWindow_MAX 20 /* DDR3 30 */
// for 0x98 index and 0x9c data for DCT0
@@ -307,60 +307,60 @@
// even at ganged mode, 0x198/0x19c will be used for channnel B
#define DRAM_CTRL_ADDI_DATA_OFFSET 0x98
-#define DCAO_DctOffset_SHIFT 0
-#define DCAO_DctOffset_MASK 0x3fffffff
-#define DCAO_DctAccessWrite (1<<30)
-#define DCAO_DctAccessDone (1<<31)
+#define DCAO_DctOffset_SHIFT 0
+#define DCAO_DctOffset_MASK 0x3fffffff
+#define DCAO_DctAccessWrite (1<<30)
+#define DCAO_DctAccessDone (1<<31)
#define DRAM_CTRL_ADDI_DATA_PORT 0x9c
#define DRAM_OUTPUT_DRV_COMP_CTRL 0x00
-#define DODCC_CkeDrvStren_SHIFT 0
-#define DODCC_CkeDrvStren_MASK 3
-#define DODCC_CkeDrvStren_1_0X 0
-#define DODCC_CkeDrvStren_1_25X 1
-#define DODCC_CkeDrvStren_1_5X 2
-#define DODCC_CkeDrvStren_2_0X 3
-#define DODCC_CsOdtDrvStren_SHIFT 4
-#define DODCC_CsOdtDrvStren_MASK 3
-#define DODCC_CsOdtDrvStren_1_0X 0
-#define DODCC_CsOdtDrvStren_1_25X 1
-#define DODCC_CsOdtDrvStren_1_5X 2
-#define DODCC_CsOdtDrvStren_2_0X 3
-#define DODCC_AddrCmdDrvStren_SHIFT 8
-#define DODCC_AddrCmdDrvStren_MASK 3
-#define DODCC_AddrCmdDrvStren_1_0X 0
-#define DODCC_AddrCmdDrvStren_1_25X 1
-#define DODCC_AddrCmdDrvStren_1_5X 2
-#define DODCC_AddrCmdDrvStren_2_0X 3
-#define DODCC_ClkDrvStren_SHIFT 12
-#define DODCC_ClkDrvStren_MASK 3
-#define DODCC_ClkDrvStren_0_75X 0
-#define DODCC_ClkDrvStren_1_0X 1
-#define DODCC_ClkDrvStren_1_25X 2
-#define DODCC_ClkDrvStren_1_5X 3
-#define DODCC_DataDrvStren_SHIFT 16
-#define DODCC_DataDrvStren_MASK 3
-#define DODCC_DataDrvStren_0_75X 0
-#define DODCC_DataDrvStren_1_0X 1
-#define DODCC_DataDrvStren_1_25X 2
-#define DODCC_DataDrvStren_1_5X 3
-#define DODCC_DqsDrvStren_SHIFT 20
-#define DODCC_DqsDrvStren_MASK 3
-#define DODCC_DqsDrvStren_0_75X 0
-#define DODCC_DqsDrvStren_1_0X 1
-#define DODCC_DqsDrvStren_1_25X 2
-#define DODCC_DqsDrvStren_1_5X 3
-#define DODCC_ProcOdt_SHIFT 28
-#define DODCC_ProcOdt_MASK 3
-#define DODCC_ProcOdt_300_OHMS 0
-#define DODCC_ProcOdt_150_OHMS 1
-#define DODCC_ProcOdt_75_OHMS 2
+#define DODCC_CkeDrvStren_SHIFT 0
+#define DODCC_CkeDrvStren_MASK 3
+#define DODCC_CkeDrvStren_1_0X 0
+#define DODCC_CkeDrvStren_1_25X 1
+#define DODCC_CkeDrvStren_1_5X 2
+#define DODCC_CkeDrvStren_2_0X 3
+#define DODCC_CsOdtDrvStren_SHIFT 4
+#define DODCC_CsOdtDrvStren_MASK 3
+#define DODCC_CsOdtDrvStren_1_0X 0
+#define DODCC_CsOdtDrvStren_1_25X 1
+#define DODCC_CsOdtDrvStren_1_5X 2
+#define DODCC_CsOdtDrvStren_2_0X 3
+#define DODCC_AddrCmdDrvStren_SHIFT 8
+#define DODCC_AddrCmdDrvStren_MASK 3
+#define DODCC_AddrCmdDrvStren_1_0X 0
+#define DODCC_AddrCmdDrvStren_1_25X 1
+#define DODCC_AddrCmdDrvStren_1_5X 2
+#define DODCC_AddrCmdDrvStren_2_0X 3
+#define DODCC_ClkDrvStren_SHIFT 12
+#define DODCC_ClkDrvStren_MASK 3
+#define DODCC_ClkDrvStren_0_75X 0
+#define DODCC_ClkDrvStren_1_0X 1
+#define DODCC_ClkDrvStren_1_25X 2
+#define DODCC_ClkDrvStren_1_5X 3
+#define DODCC_DataDrvStren_SHIFT 16
+#define DODCC_DataDrvStren_MASK 3
+#define DODCC_DataDrvStren_0_75X 0
+#define DODCC_DataDrvStren_1_0X 1
+#define DODCC_DataDrvStren_1_25X 2
+#define DODCC_DataDrvStren_1_5X 3
+#define DODCC_DqsDrvStren_SHIFT 20
+#define DODCC_DqsDrvStren_MASK 3
+#define DODCC_DqsDrvStren_0_75X 0
+#define DODCC_DqsDrvStren_1_0X 1
+#define DODCC_DqsDrvStren_1_25X 2
+#define DODCC_DqsDrvStren_1_5X 3
+#define DODCC_ProcOdt_SHIFT 28
+#define DODCC_ProcOdt_MASK 3
+#define DODCC_ProcOdt_300_OHMS 0
+#define DODCC_ProcOdt_150_OHMS 1
+#define DODCC_ProcOdt_75_OHMS 2
#if 0
//DDR3
-#define DODCC_ProcOdt_240_OHMS 0
-#define DODCC_ProcOdt_120_OHMS 1
-#define DODCC_ProcOdt_60_OHMS 2
+#define DODCC_ProcOdt_240_OHMS 0
+#define DODCC_ProcOdt_120_OHMS 1
+#define DODCC_ProcOdt_60_OHMS 2
#endif
/*
@@ -374,138 +374,138 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
*/
//02/15/2006 18:37
#define DRAM_WRITE_DATA_TIMING_CTRL_LOW 0x01
-#define DWDTC_WrDatFineDlyByte0_SHIFT 0
-#define DWDTC_WrDatFineDlyByte_MASK 0x1f
-#define DWDTC_WrDatFineDlyByte_BASE 0
-#define DWDTC_WrDatFineDlyByte_MIN 0
-#define DWDTC_WrDatFineDlyByte_MAX 31 // 1/64 MEMCLK
-#define DWDTC_WrDatGrossDlyByte0_SHIFT 5
-#define DWDTC_WrDatGrossDlyByte_MASK 0x3
-#define DWDTC_WrDatGrossDlyByte_NO_DELAY 0
-#define DWDTC_WrDatGrossDlyByte_0_5_ 1
-#define DWDTC_WrDatGrossDlyByte_1 2
-#define DWDTC_WrDatFineDlyByte1_SHIFT 8
-#define DWDTC_WrDatGrossDlyByte1_SHIFT 13
-#define DWDTC_WrDatFineDlyByte2_SHIFT 16
-#define DWDTC_WrDatGrossDlyByte2_SHIFT 21
-#define DWDTC_WrDatFineDlyByte3_SHIFT 24
-#define DWDTC_WrDatGrossDlyByte3_SHIFT 29
+#define DWDTC_WrDatFineDlyByte0_SHIFT 0
+#define DWDTC_WrDatFineDlyByte_MASK 0x1f
+#define DWDTC_WrDatFineDlyByte_BASE 0
+#define DWDTC_WrDatFineDlyByte_MIN 0
+#define DWDTC_WrDatFineDlyByte_MAX 31 // 1/64 MEMCLK
+#define DWDTC_WrDatGrossDlyByte0_SHIFT 5
+#define DWDTC_WrDatGrossDlyByte_MASK 0x3
+#define DWDTC_WrDatGrossDlyByte_NO_DELAY 0
+#define DWDTC_WrDatGrossDlyByte_0_5_ 1
+#define DWDTC_WrDatGrossDlyByte_1 2
+#define DWDTC_WrDatFineDlyByte1_SHIFT 8
+#define DWDTC_WrDatGrossDlyByte1_SHIFT 13
+#define DWDTC_WrDatFineDlyByte2_SHIFT 16
+#define DWDTC_WrDatGrossDlyByte2_SHIFT 21
+#define DWDTC_WrDatFineDlyByte3_SHIFT 24
+#define DWDTC_WrDatGrossDlyByte3_SHIFT 29
#define DRAM_WRITE_DATA_TIMING_CTRL_HIGH 0x02
-#define DWDTC_WrDatFineDlyByte4_SHIFT 0
-#define DWDTC_WrDatGrossDlyByte4_SHIFT 5
-#define DWDTC_WrDatFineDlyByte5_SHIFT 8
-#define DWDTC_WrDatGrossDlyByte5_SHIFT 13
-#define DWDTC_WrDatFineDlyByte6_SHIFT 16
-#define DWDTC_WrDatGrossDlyByte6_SHIFT 21
-#define DWDTC_WrDatFineDlyByte7_SHIFT 24
-#define DWDTC_WrDatGrossDlyByte7_SHIFT 29
+#define DWDTC_WrDatFineDlyByte4_SHIFT 0
+#define DWDTC_WrDatGrossDlyByte4_SHIFT 5
+#define DWDTC_WrDatFineDlyByte5_SHIFT 8
+#define DWDTC_WrDatGrossDlyByte5_SHIFT 13
+#define DWDTC_WrDatFineDlyByte6_SHIFT 16
+#define DWDTC_WrDatGrossDlyByte6_SHIFT 21
+#define DWDTC_WrDatFineDlyByte7_SHIFT 24
+#define DWDTC_WrDatGrossDlyByte7_SHIFT 29
#define DRAM_WRITE_ECC_TIMING_CTRL 0x03
-#define DWETC_WrChkFinDly_SHIFT 0
-#define DWETC_WrChkGrossDly_SHIFT 5
+#define DWETC_WrChkFinDly_SHIFT 0
+#define DWETC_WrChkGrossDly_SHIFT 5
#define DRAM_ADDR_CMD_TIMING_CTRL 0x04
-#define DACTC_CkeFineDelay_SHIFT 0
-#define DACTC_CkeFineDelay_MASK 0x1f
-#define DACTC_CkeFineDelay_BASE 0
-#define DACTC_CkeFineDelay_MIN 0
-#define DACTC_CkeFineDelay_MAX 31
-#define DACTC_CkeSetup (1<<5)
-#define DACTC_CsOdtFineDelay_SHIFT 8
-#define DACTC_CsOdtFineDelay_MASK 0x1f
-#define DACTC_CsOdtFineDelay_BASE 0
-#define DACTC_CsOdtFineDelay_MIN 0
-#define DACTC_CsOdtFineDelay_MAX 31
-#define DACTC_CsOdtSetup (1<<13)
-#define DACTC_AddrCmdFineDelay_SHIFT 16
-#define DACTC_AddrCmdFineDelay_MASK 0x1f
-#define DACTC_AddrCmdFineDelay_BASE 0
-#define DACTC_AddrCmdFineDelay_MIN 0
-#define DACTC_AddrCmdFineDelay_MAX 31
-#define DACTC_AddrCmdSetup (1<<21)
+#define DACTC_CkeFineDelay_SHIFT 0
+#define DACTC_CkeFineDelay_MASK 0x1f
+#define DACTC_CkeFineDelay_BASE 0
+#define DACTC_CkeFineDelay_MIN 0
+#define DACTC_CkeFineDelay_MAX 31
+#define DACTC_CkeSetup (1<<5)
+#define DACTC_CsOdtFineDelay_SHIFT 8
+#define DACTC_CsOdtFineDelay_MASK 0x1f
+#define DACTC_CsOdtFineDelay_BASE 0
+#define DACTC_CsOdtFineDelay_MIN 0
+#define DACTC_CsOdtFineDelay_MAX 31
+#define DACTC_CsOdtSetup (1<<13)
+#define DACTC_AddrCmdFineDelay_SHIFT 16
+#define DACTC_AddrCmdFineDelay_MASK 0x1f
+#define DACTC_AddrCmdFineDelay_BASE 0
+#define DACTC_AddrCmdFineDelay_MIN 0
+#define DACTC_AddrCmdFineDelay_MAX 31
+#define DACTC_AddrCmdSetup (1<<21)
#define DRAM_READ_DQS_TIMING_CTRL_LOW 0x05
-#define DRDTC_RdDqsTimeByte0_SHIFT 0
-#define DRDTC_RdDqsTimeByte_MASK 0x3f
-#define DRDTC_RdDqsTimeByte_BASE 0
-#define DRDTC_RdDqsTimeByte_MIN 0
-#define DRDTC_RdDqsTimeByte_MAX 63 // 1/128 MEMCLK
-#define DRDTC_RdDqsTimeByte1_SHIFT 8
-#define DRDTC_RdDqsTimeByte2_SHIFT 16
-#define DRDTC_RdDqsTimeByte3_SHIFT 24
+#define DRDTC_RdDqsTimeByte0_SHIFT 0
+#define DRDTC_RdDqsTimeByte_MASK 0x3f
+#define DRDTC_RdDqsTimeByte_BASE 0
+#define DRDTC_RdDqsTimeByte_MIN 0
+#define DRDTC_RdDqsTimeByte_MAX 63 // 1/128 MEMCLK
+#define DRDTC_RdDqsTimeByte1_SHIFT 8
+#define DRDTC_RdDqsTimeByte2_SHIFT 16
+#define DRDTC_RdDqsTimeByte3_SHIFT 24
#define DRAM_READ_DQS_TIMING_CTRL_HIGH 0x06
-#define DRDTC_RdDqsTimeByte4_SHIFT 0
-#define DRDTC_RdDqsTimeByte5_SHIFT 8
-#define DRDTC_RdDqsTimeByte6_SHIFT 16
-#define DRDTC_RdDqsTimeByte7_SHIFT 24
+#define DRDTC_RdDqsTimeByte4_SHIFT 0
+#define DRDTC_RdDqsTimeByte5_SHIFT 8
+#define DRDTC_RdDqsTimeByte6_SHIFT 16
+#define DRDTC_RdDqsTimeByte7_SHIFT 24
#define DRAM_READ_DQS_ECC_TIMING_CTRL 0x07
-#define DRDETC_RdDqsTimeCheck_SHIFT 0
+#define DRDETC_RdDqsTimeCheck_SHIFT 0
#define DRAM_PHY_CTRL 0x08
-#define DPC_WrtLvTrEn (1<<0)
-#define DPC_WrtLvTrMode (1<<1)
-#define DPC_TrNibbleSel (1<<2)
-#define DPC_TrDimmSel_SHIFT 4
-#define DPC_TrDimmSel_MASK 3 /* 0-->dimm0, 1-->dimm1, 2--->dimm2, 3--->dimm3 */
-#define DPC_WrLvOdt_SHIFT 8
-#define DPC_WrLvOdt_MASK 0xf /* bit 0-->odt 0, ...*/
-#define DPC_WrLvODtEn (1<<12)
-#define DPC_DqsRcvTrEn (1<<13)
-#define DPC_DisAutoComp (1<<30)
-#define DPC_AsyncCompUpdate (1<<31)
+#define DPC_WrtLvTrEn (1<<0)
+#define DPC_WrtLvTrMode (1<<1)
+#define DPC_TrNibbleSel (1<<2)
+#define DPC_TrDimmSel_SHIFT 4
+#define DPC_TrDimmSel_MASK 3 /* 0-->dimm0, 1-->dimm1, 2--->dimm2, 3--->dimm3 */
+#define DPC_WrLvOdt_SHIFT 8
+#define DPC_WrLvOdt_MASK 0xf /* bit 0-->odt 0, ...*/
+#define DPC_WrLvODtEn (1<<12)
+#define DPC_DqsRcvTrEn (1<<13)
+#define DPC_DisAutoComp (1<<30)
+#define DPC_AsyncCompUpdate (1<<31)
#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_0 0x10 //DIMM0 Channel A
-#define DDRETC_DqsRcvEnFineDelayByte0_SHIFT 0
-#define DDRETC_DqsRcvEnFineDelayByte0_MASK 0x1f
-#define DDRETC_DqsRcvEnGrossDelayByte0_SHIFT 5
-#define DDRETC_DqsRcvEnGrossDelayByte0_MASK 0x3
-#define DDRETC_DqsRcvEnFineDelayByte1_SHIFT 8
-#define DDRETC_DqsRcvEnGrossDelayByte1_SHIFT 13
-#define DDRETC_DqsRcvEnFineDelayByte2_SHIFT 16
-#define DDRETC_DqsRcvEnGrossDelayByte2_SHIFT 21
-#define DDRETC_DqsRcvEnFineDelayByte3_SHIFT 24
-#define DDRETC_DqsRcvEnGrossDelayByte3_SHIFT 29
+#define DDRETC_DqsRcvEnFineDelayByte0_SHIFT 0
+#define DDRETC_DqsRcvEnFineDelayByte0_MASK 0x1f
+#define DDRETC_DqsRcvEnGrossDelayByte0_SHIFT 5
+#define DDRETC_DqsRcvEnGrossDelayByte0_MASK 0x3
+#define DDRETC_DqsRcvEnFineDelayByte1_SHIFT 8
+#define DDRETC_DqsRcvEnGrossDelayByte1_SHIFT 13
+#define DDRETC_DqsRcvEnFineDelayByte2_SHIFT 16
+#define DDRETC_DqsRcvEnGrossDelayByte2_SHIFT 21
+#define DDRETC_DqsRcvEnFineDelayByte3_SHIFT 24
+#define DDRETC_DqsRcvEnGrossDelayByte3_SHIFT 29
#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_1 0x11 //DIMM0 Channel A
-#define DDRETC_DqsRcvEnFineDelayByte4_SHIFT 0
-#define DDRETC_DqsRcvEnGrossDelayByte4_SHIFT 5
-#define DDRETC_DqsRcvEnFineDelayByte5_SHIFT 8
-#define DDRETC_DqsRcvEnGrossDelayByte5_SHIFT 13
-#define DDRETC_DqsRcvEnFineDelayByte6_SHIFT 16
-#define DDRETC_DqsRcvEnGrossDelayByte6_SHIFT 21
-#define DDRETC_DqsRcvEnFineDelayByte7_SHIFT 24
-#define DDRETC_DqsRcvEnGrossDelayByte7_SHIFT 29
+#define DDRETC_DqsRcvEnFineDelayByte4_SHIFT 0
+#define DDRETC_DqsRcvEnGrossDelayByte4_SHIFT 5
+#define DDRETC_DqsRcvEnFineDelayByte5_SHIFT 8
+#define DDRETC_DqsRcvEnGrossDelayByte5_SHIFT 13
+#define DDRETC_DqsRcvEnFineDelayByte6_SHIFT 16
+#define DDRETC_DqsRcvEnGrossDelayByte6_SHIFT 21
+#define DDRETC_DqsRcvEnFineDelayByte7_SHIFT 24
+#define DDRETC_DqsRcvEnGrossDelayByte7_SHIFT 29
#define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_0_0 0x12
-#define DDRETCE_WrChkFineDlyByte0_SHIFT 0
-#define DDRETCE_WrChkGrossDlyByte0_SHIFT 5
+#define DDRETCE_WrChkFineDlyByte0_SHIFT 0
+#define DDRETCE_WrChkGrossDlyByte0_SHIFT 5
#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_2 0x20 //DIMM0 channel B
-#define DDRETC_DqsRcvEnFineDelayByte8_SHIFT 0
-#define DDRETC_DqsRcvEnGrossDelayByte8_SHIFT 5
-#define DDRETC_DqsRcvEnFineDelayByte9_SHIFT 8
-#define DDRETC_DqsRcvEnGrossDelayByte9_SHIFT 13
-#define DDRETC_DqsRcvEnFineDelayByte10_SHIFT 16
-#define DDRETC_DqsRcvEnGrossDelayByte10_SHIFT 21
-#define DDRETC_DqsRcvEnFineDelayByte11_SHIFT 24
-#define DDRETC_DqsRcvEnGrossDelayByte11_SHIFT 29
+#define DDRETC_DqsRcvEnFineDelayByte8_SHIFT 0
+#define DDRETC_DqsRcvEnGrossDelayByte8_SHIFT 5
+#define DDRETC_DqsRcvEnFineDelayByte9_SHIFT 8
+#define DDRETC_DqsRcvEnGrossDelayByte9_SHIFT 13
+#define DDRETC_DqsRcvEnFineDelayByte10_SHIFT 16
+#define DDRETC_DqsRcvEnGrossDelayByte10_SHIFT 21
+#define DDRETC_DqsRcvEnFineDelayByte11_SHIFT 24
+#define DDRETC_DqsRcvEnGrossDelayByte11_SHIFT 29
#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_3 0x21 // DIMM0 Channel B
-#define DDRETC_DqsRcvEnFineDelayByte12_SHIFT 0
-#define DDRETC_DqsRcvEnGrossDelayByte12_SHIFT 5
-#define DDRETC_DqsRcvEnFineDelayByte13_SHIFT 8
-#define DDRETC_DqsRcvEnGrossDelayByte13_SHIFT 13
-#define DDRETC_DqsRcvEnFineDelayByte14_SHIFT 16
-#define DDRETC_DqsRcvEnGrossDelayByte14_SHIFT 21
-#define DDRETC_DqsRcvEnFineDelayByte15_SHIFT 24
-#define DDRETC_DqsRcvEnGrossDelayByte15_SHIFT 29
+#define DDRETC_DqsRcvEnFineDelayByte12_SHIFT 0
+#define DDRETC_DqsRcvEnGrossDelayByte12_SHIFT 5
+#define DDRETC_DqsRcvEnFineDelayByte13_SHIFT 8
+#define DDRETC_DqsRcvEnGrossDelayByte13_SHIFT 13
+#define DDRETC_DqsRcvEnFineDelayByte14_SHIFT 16
+#define DDRETC_DqsRcvEnGrossDelayByte14_SHIFT 21
+#define DDRETC_DqsRcvEnFineDelayByte15_SHIFT 24
+#define DDRETC_DqsRcvEnGrossDelayByte15_SHIFT 29
#define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_0_1 0x22
-#define DDRETCE_WrChkFineDlyByte1_SHIFT 0
-#define DDRETCE_WrChkGrossDlyByte1_SHIFT 5
+#define DDRETCE_WrChkFineDlyByte1_SHIFT 0
+#define DDRETCE_WrChkGrossDlyByte1_SHIFT 5
#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_0 0x13 //DIMM1
#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_1 0x14
@@ -533,54 +533,54 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
#if 0
//DDR3
#define DRAM_DQS_WRITE_TIME_CTRL_0_0 0x30 //DIMM0 Channel A
-#define DDWTC_WrDqsFineDlyByte0_SHIFT 0
-#define DDWTC_WrDqsFineDlyByte0_MASK 0x1f
-#define DDWTC_WrDqsGrossDlyByte0_SHIFT 5
-#define DDWTC_WrDqsGrossDlyByte0_MASK 0x3
-#define DDWTC_WrDqsFineDlyByte1_SHIFT 8
-#define DDWTC_WrDqsGrossDlyByte1_SHIFT 13
-#define DDWTC_WrDqsFineDlyByte2_SHIFT 16
-#define DDWTC_WrDqsGrossDlyByte2_SHIFT 21
-#define DDWTC_WrDqsFineDlyByte3_SHIFT 24
-#define DDWTC_WrDqsGrossDlyByte3_SHIFT 29
+#define DDWTC_WrDqsFineDlyByte0_SHIFT 0
+#define DDWTC_WrDqsFineDlyByte0_MASK 0x1f
+#define DDWTC_WrDqsGrossDlyByte0_SHIFT 5
+#define DDWTC_WrDqsGrossDlyByte0_MASK 0x3
+#define DDWTC_WrDqsFineDlyByte1_SHIFT 8
+#define DDWTC_WrDqsGrossDlyByte1_SHIFT 13
+#define DDWTC_WrDqsFineDlyByte2_SHIFT 16
+#define DDWTC_WrDqsGrossDlyByte2_SHIFT 21
+#define DDWTC_WrDqsFineDlyByte3_SHIFT 24
+#define DDWTC_WrDqsGrossDlyByte3_SHIFT 29
#define DRAM_DQS_WRTIE_TIME_CTRL_0_1 0x31 //DIMM0 Channel A
-#define DDWTC_WrDqsFineDlyByte4_SHIFT 0
-#define DDWTC_WrDqsGrossDlyByte4_SHIFT 5
-#define DDWTC_WrDqsFineDlyByte5_SHIFT 8
-#define DDWTC_WrDqsGrossDlyByte5_SHIFT 13
-#define DDWTC_WrDqsFineDlyByte6_SHIFT 16
-#define DDWTC_WrDqsGrossDlyByte6_SHIFT 21
-#define DDWTC_WrDqsFineDlyByte7_SHIFT 24
-#define DDWTC_WrDqsGrossDlyByte7_SHIFT 29
+#define DDWTC_WrDqsFineDlyByte4_SHIFT 0
+#define DDWTC_WrDqsGrossDlyByte4_SHIFT 5
+#define DDWTC_WrDqsFineDlyByte5_SHIFT 8
+#define DDWTC_WrDqsGrossDlyByte5_SHIFT 13
+#define DDWTC_WrDqsFineDlyByte6_SHIFT 16
+#define DDWTC_WrDqsGrossDlyByte6_SHIFT 21
+#define DDWTC_WrDqsFineDlyByte7_SHIFT 24
+#define DDWTC_WrDqsGrossDlyByte7_SHIFT 29
#define DRAM_DQS_WRITE_TIMING_CTRL_ECC_0_0 0x32
-#define DDWTCE_WrDqsChkFineDlyByte0_SHIFT 0
-#define DDWTCE_WrDqsChkGrossDlyByte0_SHIFT 5
+#define DDWTCE_WrDqsChkFineDlyByte0_SHIFT 0
+#define DDWTCE_WrDqsChkGrossDlyByte0_SHIFT 5
#define DRAM_DQS_WRITE_TIME_CTRL_0_2 0x40 //DIMM0 Channel B
-#define DDWTC_WrDqsFineDlyByte8_SHIFT 0
-#define DDWTC_WrDqsGrossDlyByte8_SHIFT 5
-#define DDWTC_WrDqsFineDlyByte9_SHIFT 8
-#define DDWTC_WrDqsGrossDlyByte9_SHIFT 13
-#define DDWTC_WrDqsFineDlyByte10_SHIFT 16
-#define DDWTC_WrDqsGrossDlyByte10_SHIFT 21
-#define DDWTC_WrDqsFineDlyByte11_SHIFT 24
-#define DDWTC_WrDqsGrossDlyByte11_SHIFT 29
+#define DDWTC_WrDqsFineDlyByte8_SHIFT 0
+#define DDWTC_WrDqsGrossDlyByte8_SHIFT 5
+#define DDWTC_WrDqsFineDlyByte9_SHIFT 8
+#define DDWTC_WrDqsGrossDlyByte9_SHIFT 13
+#define DDWTC_WrDqsFineDlyByte10_SHIFT 16
+#define DDWTC_WrDqsGrossDlyByte10_SHIFT 21
+#define DDWTC_WrDqsFineDlyByte11_SHIFT 24
+#define DDWTC_WrDqsGrossDlyByte11_SHIFT 29
#define DRAM_DQS_WRTIE_TIME_CTRL_0_3 0x41 //DIMM0 Channel B
-#define DDWTC_WrDqsFineDlyByte12_SHIFT 0
-#define DDWTC_WrDqsGrossDlyByte12_SHIFT 5
-#define DDWTC_WrDqsFineDlyByte13_SHIFT 8
-#define DDWTC_WrDqsGrossDlyByte13_SHIFT 13
-#define DDWTC_WrDqsFineDlyByte14_SHIFT 16
-#define DDWTC_WrDqsGrossDlyByte14_SHIFT 21
-#define DDWTC_WrDqsFineDlyByte15_SHIFT 24
-#define DDWTC_WrDqsGrossDlyByte15_SHIFT 29
+#define DDWTC_WrDqsFineDlyByte12_SHIFT 0
+#define DDWTC_WrDqsGrossDlyByte12_SHIFT 5
+#define DDWTC_WrDqsFineDlyByte13_SHIFT 8
+#define DDWTC_WrDqsGrossDlyByte13_SHIFT 13
+#define DDWTC_WrDqsFineDlyByte14_SHIFT 16
+#define DDWTC_WrDqsGrossDlyByte14_SHIFT 21
+#define DDWTC_WrDqsFineDlyByte15_SHIFT 24
+#define DDWTC_WrDqsGrossDlyByte15_SHIFT 29
#define DRAM_DQS_WRITE_TIMING_CTRL_ECC_0_1 0x42
-#define DDWTCE_WrDqsChkFineDlyByte1_SHIFT 0
-#define DDWTCE_WrDqsChkGrossDlyByte1_SHIFT 5
+#define DDWTCE_WrDqsChkFineDlyByte1_SHIFT 0
+#define DDWTCE_WrDqsChkGrossDlyByte1_SHIFT 5
#define DRAM_DQS_WRITE_TIME_CTRL_1_0 0x33 //DIMM1 Channel A
#define DRAM_DQS_WRTIE_TIME_CTRL_1_1 0x34 //DIMM1 Channel A
@@ -591,230 +591,230 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
#endif
#define DRAM_PHASE_RECOVERY_CTRL_0 0x50
-#define DPRC_PhRecFineDlyByte0_SHIFT 0
-#define DDWTC_PhRecFineDlyByte0_MASK 0x1f
-#define DDWTC_PhRecGrossDlyByte0_SHIFT 5
-#define DDWTC_PhRecGrossDlyByte0_MASK 0x3
-#define DDWTC_PhRecFineDlyByte1_SHIFT 8
-#define DDWTC_PhRecGrossDlyByte1_SHIFT 13
-#define DDWTC_PhRecFineDlyByte2_SHIFT 16
-#define DDWTC_PhRecGrossDlyByte2_SHIFT 21
-#define DDWTC_PhRecFineDlyByte3_SHIFT 24
-#define DDWTC_PhRecGrossDlyByte3_SHIFT 29
+#define DPRC_PhRecFineDlyByte0_SHIFT 0
+#define DDWTC_PhRecFineDlyByte0_MASK 0x1f
+#define DDWTC_PhRecGrossDlyByte0_SHIFT 5
+#define DDWTC_PhRecGrossDlyByte0_MASK 0x3
+#define DDWTC_PhRecFineDlyByte1_SHIFT 8
+#define DDWTC_PhRecGrossDlyByte1_SHIFT 13
+#define DDWTC_PhRecFineDlyByte2_SHIFT 16
+#define DDWTC_PhRecGrossDlyByte2_SHIFT 21
+#define DDWTC_PhRecFineDlyByte3_SHIFT 24
+#define DDWTC_PhRecGrossDlyByte3_SHIFT 29
#define DRAM_PHASE_RECOVERY_CTRL_1 0x51
-#define DPRC_PhRecFineDlyByte4_SHIFT 0
-#define DDWTC_PhRecGrossDlyByte4_SHIFT 5
-#define DDWTC_PhRecFineDlyByte5_SHIFT 8
-#define DDWTC_PhRecGrossDlyByte5_SHIFT 13
-#define DDWTC_PhRecFineDlyByte6_SHIFT 16
-#define DDWTC_PhRecGrossDlyByte6_SHIFT 21
-#define DDWTC_PhRecFineDlyByte7_SHIFT 24
-#define DDWTC_PhRecGrossDlyByte7_SHIFT 29
+#define DPRC_PhRecFineDlyByte4_SHIFT 0
+#define DDWTC_PhRecGrossDlyByte4_SHIFT 5
+#define DDWTC_PhRecFineDlyByte5_SHIFT 8
+#define DDWTC_PhRecGrossDlyByte5_SHIFT 13
+#define DDWTC_PhRecFineDlyByte6_SHIFT 16
+#define DDWTC_PhRecGrossDlyByte6_SHIFT 21
+#define DDWTC_PhRecFineDlyByte7_SHIFT 24
+#define DDWTC_PhRecGrossDlyByte7_SHIFT 29
#define DRAM_ECC_PHASE_RECOVERY_CTRL 0x52
-#define DEPRC_PhRecEccDlyByte0_SHIFT 0
-#define DEPRC_PhRecEccGrossDlyByte0_SHIFT 5
+#define DEPRC_PhRecEccDlyByte0_SHIFT 0
+#define DEPRC_PhRecEccGrossDlyByte0_SHIFT 5
#define DRAM_WRITE_LEVEL_ERROR 0x53 /* read only */
-#define DWLE_WrLvErr_SHIFT 0
-#define DWLE_WrLvErr_MASK 0xff
+#define DWLE_WrLvErr_SHIFT 0
+#define DWLE_WrLvErr_MASK 0xff
#define DRAM_CTRL_MISC 0xa0
-#define DCM_MemCleared (1<<0) /* RD == F2x110 [MemCleared] */
-#define DCM_DramEnabled (1<<9) /* RD == F2x110 [DramEnabled] */
+#define DCM_MemCleared (1<<0) /* RD == F2x110 [MemCleared] */
+#define DCM_DramEnabled (1<<9) /* RD == F2x110 [DramEnabled] */
#define NB_TIME_STAMP_COUNT_LOW 0xb0
-#define TscLow_SHIFT 0
-#define TscLow_MASK 0xffffffff
+#define TscLow_SHIFT 0
+#define TscLow_MASK 0xffffffff
#define NB_TIME_STAMP_COUNT_HIGH 0xb4
-#define TscHigh_SHIFT 0
-#define TscHigh_Mask 0xff
+#define TscHigh_SHIFT 0
+#define TscHigh_Mask 0xff
#define DCT_DEBUG_CTRL 0xf0 /* 0xf0 for DCT0, 0x1f0 is for DCT1*/
-#define DDC_DllAdjust_SHIFT 0
-#define DDC_DllAdjust_MASK 0xff
-#define DDC_DllSlower (1<<8)
-#define DDC_DllFaster (1<<9)
-#define DDC_WrtDqsAdjust_SHIFT 16
-#define DDC_WrtDqsAdjust_MASK 0x7
-#define DDC_WrtDqsAdjustEn (1<<19)
+#define DDC_DllAdjust_SHIFT 0
+#define DDC_DllAdjust_MASK 0xff
+#define DDC_DllSlower (1<<8)
+#define DDC_DllFaster (1<<9)
+#define DDC_WrtDqsAdjust_SHIFT 16
+#define DDC_WrtDqsAdjust_MASK 0x7
+#define DDC_WrtDqsAdjustEn (1<<19)
#define DRAM_CTRL_SEL_LOW 0x110
-#define DCSL_DctSelHiRngEn (1<<0)
-#define DCSL_DctSelHi (1<<1)
-#define DCSL_DctSelIntLvEn (1<<2)
-#define DCSL_MemClrInit (1<<3) /* WR only */
-#define DCSL_DctGangEn (1<<4)
-#define DCSL_DctDataIntLv (1<<5)
-#define DCSL_DctSelIntLvAddr_SHIFT
-#define DCSL_DctSelIntLvAddr_MASK 3
-#define DCSL_DramEnable (1<<8) /* RD only */
-#define DCSL_MemClrBusy (1<<9) /* RD only */
-#define DCSL_MemCleared (1<<10) /* RD only */
-#define DCSL_DctSelBaseAddr_47_27_SHIFT 11
-#define DCSL_DctSelBaseAddr_47_27_MASK 0x1fffff
+#define DCSL_DctSelHiRngEn (1<<0)
+#define DCSL_DctSelHi (1<<1)
+#define DCSL_DctSelIntLvEn (1<<2)
+#define DCSL_MemClrInit (1<<3) /* WR only */
+#define DCSL_DctGangEn (1<<4)
+#define DCSL_DctDataIntLv (1<<5)
+#define DCSL_DctSelIntLvAddr_SHIFT
+#define DCSL_DctSelIntLvAddr_MASK 3
+#define DCSL_DramEnable (1<<8) /* RD only */
+#define DCSL_MemClrBusy (1<<9) /* RD only */
+#define DCSL_MemCleared (1<<10) /* RD only */
+#define DCSL_DctSelBaseAddr_47_27_SHIFT 11
+#define DCSL_DctSelBaseAddr_47_27_MASK 0x1fffff
#define DRAM_CTRL_SEL_HIGH 0x114
-#define DCSH_DctSelBaseOffset_47_26_SHIFT 10
-#define DCSH_DctSelBaseOffset_47_26_MASK 0x3fffff
+#define DCSH_DctSelBaseOffset_47_26_SHIFT 10
+#define DCSH_DctSelBaseOffset_47_26_MASK 0x3fffff
#define MEM_CTRL_CONF_LOW 0x118
-#define MCCL_MctPriCpuRd (1<<0)
-#define MCCL_MctPriCpuWr (1<<1)
-#define MCCL_MctPriIsocRd_SHIFT 4
-#define MCCL_MctPriIsoc_MASK 0x3
-#define MCCL_MctPriIsocWr_SHIFT 6
-#define MCCL_MctPriIsocWe_MASK 0x3
-#define MCCL_MctPriDefault_SHIFT 8
-#define MCCL_MctPriDefault_MASK 0x3
-#define MCCL_MctPriWr_SHIFT 10
-#define MCCL_MctPriWr_MASK 0x3
-#define MCCL_MctPriIsoc_SHIFT 12
-#define MCCL_MctPriIsoc_MASK 0x3
-#define MCCL_MctPriTrace_SHIFT 14
-#define MCCL_MctPriTrace_MASK 0x3
-#define MCCL_MctPriScrub_SHIFT 16
-#define MCCL_MctPriScrub_MASK 0x3
-#define MCCL_McqMedPriByPassMax_SHIFT 20
-#define MCCL_McqMedPriByPassMax_MASK 0x7
-#define MCCL_McqHiPriByPassMax_SHIFT 24
-#define MCCL_McqHiPriByPassMax_MASK 0x7
-#define MCCL_MctVarPriCntLmt_SHIFT 28
-#define MCCL_MctVarPriCntLmt_MASK 0x7
+#define MCCL_MctPriCpuRd (1<<0)
+#define MCCL_MctPriCpuWr (1<<1)
+#define MCCL_MctPriIsocRd_SHIFT 4
+#define MCCL_MctPriIsoc_MASK 0x3
+#define MCCL_MctPriIsocWr_SHIFT 6
+#define MCCL_MctPriIsocWe_MASK 0x3
+#define MCCL_MctPriDefault_SHIFT 8
+#define MCCL_MctPriDefault_MASK 0x3
+#define MCCL_MctPriWr_SHIFT 10
+#define MCCL_MctPriWr_MASK 0x3
+#define MCCL_MctPriIsoc_SHIFT 12
+#define MCCL_MctPriIsoc_MASK 0x3
+#define MCCL_MctPriTrace_SHIFT 14
+#define MCCL_MctPriTrace_MASK 0x3
+#define MCCL_MctPriScrub_SHIFT 16
+#define MCCL_MctPriScrub_MASK 0x3
+#define MCCL_McqMedPriByPassMax_SHIFT 20
+#define MCCL_McqMedPriByPassMax_MASK 0x7
+#define MCCL_McqHiPriByPassMax_SHIFT 24
+#define MCCL_McqHiPriByPassMax_MASK 0x7
+#define MCCL_MctVarPriCntLmt_SHIFT 28
+#define MCCL_MctVarPriCntLmt_MASK 0x7
#define MEM_CTRL_CONF_HIGH 0x11c
-#define MCCH_DctWrLimit_SHIFT 0
-#define MCCH_DctWrLimit_MASK 0x3
-#define MCCH_MctWrLimit_SHIFT 2
-#define MCCH_MctWrLimit_MASK 0x1f
-#define MCCH_MctPrefReqLimit_SHIFT 7
-#define MCCH_MctPrefReqLimit_MASK 0x1f
-#define MCCH_PrefCpuDis (1<<12)
-#define MCCH_PrefIoDis (1<<13)
-#define MCCH_PrefIoFixStrideEn (1<<14)
-#define MCCH_PrefFixStrideEn (1<<15)
-#define MCCH_PrefFixDist_SHIFT 16
-#define MCCH_PrefFixDist_MASK 0x3
-#define MCCH_PrefConfSat_SHIFT 18
-#define MCCH_PrefConfSat_MASK 0x3
-#define MCCH_PrefOneConf_SHIFT 20
-#define MCCH_PrefOneConf_MASK 0x3
-#define MCCH_PrefTwoConf_SHIFT 22
-#define MCCH_PrefTwoConf_MASK 0x7
-#define MCCH_PrefThreeConf_SHIFT 25
-#define MCCH_prefThreeConf_MASK 0x7
-#define MCCH_PrefDramTrainMode (1<<28)
-#define MCCH_FlushWrOnStpGnt (1<<29)
-#define MCCH_FlushWr (1<<30)
-#define MCCH_MctScrubEn (1<<31)
+#define MCCH_DctWrLimit_SHIFT 0
+#define MCCH_DctWrLimit_MASK 0x3
+#define MCCH_MctWrLimit_SHIFT 2
+#define MCCH_MctWrLimit_MASK 0x1f
+#define MCCH_MctPrefReqLimit_SHIFT 7
+#define MCCH_MctPrefReqLimit_MASK 0x1f
+#define MCCH_PrefCpuDis (1<<12)
+#define MCCH_PrefIoDis (1<<13)
+#define MCCH_PrefIoFixStrideEn (1<<14)
+#define MCCH_PrefFixStrideEn (1<<15)
+#define MCCH_PrefFixDist_SHIFT 16
+#define MCCH_PrefFixDist_MASK 0x3
+#define MCCH_PrefConfSat_SHIFT 18
+#define MCCH_PrefConfSat_MASK 0x3
+#define MCCH_PrefOneConf_SHIFT 20
+#define MCCH_PrefOneConf_MASK 0x3
+#define MCCH_PrefTwoConf_SHIFT 22
+#define MCCH_PrefTwoConf_MASK 0x7
+#define MCCH_PrefThreeConf_SHIFT 25
+#define MCCH_prefThreeConf_MASK 0x7
+#define MCCH_PrefDramTrainMode (1<<28)
+#define MCCH_FlushWrOnStpGnt (1<<29)
+#define MCCH_FlushWr (1<<30)
+#define MCCH_MctScrubEn (1<<31)
/* Function 3 */
#define MCA_NB_CONTROL 0x40
-#define MNCT_CorrEccEn (1<<0)
-#define MNCT_UnCorrEccEn (1<<1)
-#define MNCT_CrcErr0En (1<<2) /* Link 0 */
-#define MNCT_CrcErr1En (1<<3)
-#define MNCT_CrcErr2En (1<<4)
-#define MBCT_SyncPkt0En (1<<5) /* Link 0 */
-#define MBCT_SyncPkt1En (1<<6)
-#define MBCT_SyncPkt2En (1<<7)
-#define MBCT_MstrAbrtEn (1<<8)
-#define MBCT_TgtAbrtEn (1<<9)
-#define MBCT_GartTblEkEn (1<<10)
-#define MBCT_AtomicRMWEn (1<<11)
-#define MBCT_WdogTmrRptEn (1<<12)
-#define MBCT_DevErrEn (1<<13)
-#define MBCT_L3ArrayCorEn (1<<14)
-#define MBCT_L3ArrayUncEn (1<<15)
-#define MBCT_HtProtEn (1<<16)
-#define MBCT_HtDataEn (1<<17)
-#define MBCT_DramParEn (1<<18)
-#define MBCT_RtryHt0En (1<<19) /* Link 0 */
-#define MBCT_RtryHt1En (1<<20)
-#define MBCT_RtryHt2En (1<<21)
-#define MBCT_RtryHt3En (1<<22)
-#define MBCT_CrcErr3En (1<<23) /* Link 3*/
-#define MBCT_SyncPkt3En (1<<24) /* Link 4 */
-#define MBCT_McaUsPwDatErrEn (1<<25)
-#define MBCT_NbArrayParEn (1<<26)
-#define MBCT_TblWlkDatErrEn (1<<27)
-#define MBCT_FbDimmCorErrEn (1<<28)
-#define MBCT_FbDimmUnCorErrEn (1<<29)
+#define MNCT_CorrEccEn (1<<0)
+#define MNCT_UnCorrEccEn (1<<1)
+#define MNCT_CrcErr0En (1<<2) /* Link 0 */
+#define MNCT_CrcErr1En (1<<3)
+#define MNCT_CrcErr2En (1<<4)
+#define MBCT_SyncPkt0En (1<<5) /* Link 0 */
+#define MBCT_SyncPkt1En (1<<6)
+#define MBCT_SyncPkt2En (1<<7)
+#define MBCT_MstrAbrtEn (1<<8)
+#define MBCT_TgtAbrtEn (1<<9)
+#define MBCT_GartTblEkEn (1<<10)
+#define MBCT_AtomicRMWEn (1<<11)
+#define MBCT_WdogTmrRptEn (1<<12)
+#define MBCT_DevErrEn (1<<13)
+#define MBCT_L3ArrayCorEn (1<<14)
+#define MBCT_L3ArrayUncEn (1<<15)
+#define MBCT_HtProtEn (1<<16)
+#define MBCT_HtDataEn (1<<17)
+#define MBCT_DramParEn (1<<18)
+#define MBCT_RtryHt0En (1<<19) /* Link 0 */
+#define MBCT_RtryHt1En (1<<20)
+#define MBCT_RtryHt2En (1<<21)
+#define MBCT_RtryHt3En (1<<22)
+#define MBCT_CrcErr3En (1<<23) /* Link 3*/
+#define MBCT_SyncPkt3En (1<<24) /* Link 4 */
+#define MBCT_McaUsPwDatErrEn (1<<25)
+#define MBCT_NbArrayParEn (1<<26)
+#define MBCT_TblWlkDatErrEn (1<<27)
+#define MBCT_FbDimmCorErrEn (1<<28)
+#define MBCT_FbDimmUnCorErrEn (1<<29)
#define MCA_NB_CONFIG 0x44
-#define MNC_CpuRdDatErrEn (1<<1)
-#define MNC_SyncOnUcEccEn (1<<2)
-#define MNC_SynvPktGenDis (1<<3)
-#define MNC_SyncPktPropDis (1<<4)
-#define MNC_IoMstAbortDis (1<<5)
-#define MNC_CpuErrDis (1<<6)
-#define MNC_IoErrDis (1<<7)
-#define MNC_WdogTmrDis (1<<8)
-#define MNC_WdogTmrCntSel_2_0_SHIFT 9 /* 3 is ar f3x180 */
-#define MNC_WdogTmrCntSel_2_0_MASK 0x3
-#define MNC_WdogTmrBaseSel_SHIFT 12
-#define MNC_WdogTmrBaseSel_MASK 0x3
-#define MNC_LdtLinkSel_SHIFT 14
-#define MNC_LdtLinkSel_MASK 0x3
-#define MNC_GenCrcErrByte0 (1<<16)
-#define MNC_GenCrcErrByte1 (1<<17)
-#define MNC_SubLinkSel_SHIFT 18
-#define MNC_SubLinkSel_MASK 0x3
-#define MNC_SyncOnWdogEn (1<<20)
-#define MNC_SyncOnAnyErrEn (1<<21)
-#define MNC_DramEccEn (1<<22)
-#define MNC_ChipKillEccEn (1<<23)
-#define MNC_IoRdDatErrEn (1<<24)
-#define MNC_DisPciCfgCpuErrRsp (1<<25)
-#define MNC_CorrMcaExcEn (1<<26)
-#define MNC_NbMcaToMstCpuEn (1<<27)
-#define MNC_DisTgtAbtCpuErrRsp (1<<28)
-#define MNC_DisMstAbtCpuErrRsp (1<<29)
-#define MNC_SyncOnDramAdrParErrEn (1<<30)
-#define MNC_NbMcaLogEn (1<<31)
+#define MNC_CpuRdDatErrEn (1<<1)
+#define MNC_SyncOnUcEccEn (1<<2)
+#define MNC_SynvPktGenDis (1<<3)
+#define MNC_SyncPktPropDis (1<<4)
+#define MNC_IoMstAbortDis (1<<5)
+#define MNC_CpuErrDis (1<<6)
+#define MNC_IoErrDis (1<<7)
+#define MNC_WdogTmrDis (1<<8)
+#define MNC_WdogTmrCntSel_2_0_SHIFT 9 /* 3 is ar f3x180 */
+#define MNC_WdogTmrCntSel_2_0_MASK 0x3
+#define MNC_WdogTmrBaseSel_SHIFT 12
+#define MNC_WdogTmrBaseSel_MASK 0x3
+#define MNC_LdtLinkSel_SHIFT 14
+#define MNC_LdtLinkSel_MASK 0x3
+#define MNC_GenCrcErrByte0 (1<<16)
+#define MNC_GenCrcErrByte1 (1<<17)
+#define MNC_SubLinkSel_SHIFT 18
+#define MNC_SubLinkSel_MASK 0x3
+#define MNC_SyncOnWdogEn (1<<20)
+#define MNC_SyncOnAnyErrEn (1<<21)
+#define MNC_DramEccEn (1<<22)
+#define MNC_ChipKillEccEn (1<<23)
+#define MNC_IoRdDatErrEn (1<<24)
+#define MNC_DisPciCfgCpuErrRsp (1<<25)
+#define MNC_CorrMcaExcEn (1<<26)
+#define MNC_NbMcaToMstCpuEn (1<<27)
+#define MNC_DisTgtAbtCpuErrRsp (1<<28)
+#define MNC_DisMstAbtCpuErrRsp (1<<29)
+#define MNC_SyncOnDramAdrParErrEn (1<<30)
+#define MNC_NbMcaLogEn (1<<31)
#define MCA_NB_STATUS_LOW 0x48
-#define MNSL_ErrorCode_SHIFT 0
-#define MNSL_ErrorCode_MASK 0xffff
-#define MNSL_ErrorCodeExt_SHIFT 16
-#define MNSL_ErrorCodeExt_MASK 0x1f
-#define MNSL_Syndrome_15_8_SHIFT 24
-#define MNSL_Syndrome_15_8_MASK 0xff
+#define MNSL_ErrorCode_SHIFT 0
+#define MNSL_ErrorCode_MASK 0xffff
+#define MNSL_ErrorCodeExt_SHIFT 16
+#define MNSL_ErrorCodeExt_MASK 0x1f
+#define MNSL_Syndrome_15_8_SHIFT 24
+#define MNSL_Syndrome_15_8_MASK 0xff
#define MCA_NB_STATUS_HIGH 0x4c
-#define MNSH_ErrCPU_SHIFT 0
-#define MNSH_ErrCPU_MASK 0xf
-#define MNSH_LDTLink_SHIFT 4
-#define MNSH_LDTLink_MASK 0xf
-#define MNSH_ErrScrub (1<<8)
-#define MNSH_SubLink (1<<9)
-#define MNSH_McaStatusSubCache_SHIFT 10
-#define MNSH_McaStatusSubCache_MASK 0x3
-#define MNSH_Deffered (1<<12)
-#define MNSH_UnCorrECC (1<<13)
-#define MNSH_CorrECC (1<<14)
-#define MNSH_Syndrome_7_0_SHIFT 15
-#define MNSH_Syndrome_7_0_MASK 0xff
-#define MNSH_PCC (1<<25)
-#define MNSH_ErrAddrVal (1<<26)
-#define MNSH_ErrMiscVal (1<<27)
-#define MNSH_ErrEn (1<<28)
-#define MNSH_ErrUnCorr (1<<29)
-#define MNSH_ErrOver (1<<30)
-#define MNSH_ErrValid (1<<31)
+#define MNSH_ErrCPU_SHIFT 0
+#define MNSH_ErrCPU_MASK 0xf
+#define MNSH_LDTLink_SHIFT 4
+#define MNSH_LDTLink_MASK 0xf
+#define MNSH_ErrScrub (1<<8)
+#define MNSH_SubLink (1<<9)
+#define MNSH_McaStatusSubCache_SHIFT 10
+#define MNSH_McaStatusSubCache_MASK 0x3
+#define MNSH_Deffered (1<<12)
+#define MNSH_UnCorrECC (1<<13)
+#define MNSH_CorrECC (1<<14)
+#define MNSH_Syndrome_7_0_SHIFT 15
+#define MNSH_Syndrome_7_0_MASK 0xff
+#define MNSH_PCC (1<<25)
+#define MNSH_ErrAddrVal (1<<26)
+#define MNSH_ErrMiscVal (1<<27)
+#define MNSH_ErrEn (1<<28)
+#define MNSH_ErrUnCorr (1<<29)
+#define MNSH_ErrOver (1<<30)
+#define MNSH_ErrValid (1<<31)
#define MCA_NB_ADDR_LOW 0x50
-#define MNAL_ErrAddr_31_1_SHIFT 1
-#define MNAL_ErrAddr_31_1_MASK 0x7fffffff
+#define MNAL_ErrAddr_31_1_SHIFT 1
+#define MNAL_ErrAddr_31_1_MASK 0x7fffffff
#define MCA_NB_ADDR_HIGH 0x54
-#define MNAL_ErrAddr_47_32_SHIFT 0
-#define MNAL_ErrAddr_47_32_MASK 0xffff
+#define MNAL_ErrAddr_47_32_SHIFT 0
+#define MNAL_ErrAddr_47_32_MASK 0xffff
#define DRAM_SCRUB_RATE_CTRL 0x58
#define SCRUB_NONE 0
@@ -850,13 +850,13 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
#define DSRC_L3Scrub_MASK 0x1f
#define DRAM_SCRUB_ADDR_LOW 0x5C
-#define DSAL_ScrubReDirEn (1<<0)
-#define DSAL_ScrubAddrLo_SHIFT 6
-#define DSAL_ScrubAddrLo_MASK 0x3ffffff
+#define DSAL_ScrubReDirEn (1<<0)
+#define DSAL_ScrubAddrLo_SHIFT 6
+#define DSAL_ScrubAddrLo_MASK 0x3ffffff
#define DRAM_SCRUB_ADDR_HIGH 0x60
-#define DSAH_ScrubAddrHi_SHIFT 0
-#define DSAH_ScrubAddrHi_MASK 0xffff
+#define DSAH_ScrubAddrHi_SHIFT 0
+#define DSAH_ScrubAddrHi_MASK 0xffff
#define HW_THERMAL_CTRL 0x64
@@ -920,21 +920,21 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
#define NBCAP_DdrMaxRate_8_0G 2
#define NBCAP_DdrMaxRate_9_6G 1
#define NBCAP_Mem_ctrl_cap (1 << 8)
-#define MBCAP_SVMCap (1<<9)
-#define NBCAP_HtcCap (1<<10)
-#define NBCAP_CmpCap_SHIFT 12
-#define NBCAP_CmpCap_MASK 3
-#define NBCAP_MpCap_SHIFT 16
-#define NBCAP_MpCap_MASK 7
-#define NBCAP_MpCap_1N 7
-#define NBCAP_MpCap_2N 6
-#define NBCAP_MpCap_4N 5
-#define NBCAP_MpCap_8N 4
-#define NBCAP_MpCap_32N 0
-#define NBCAP_UnGangEn_SHIFT 20
-#define NBCAP_UnGangEn_MASK 0xf
-#define NBCAP_L3Cap (1<<25)
-#define NBCAP_HtAcCap (1<<26)
+#define MBCAP_SVMCap (1<<9)
+#define NBCAP_HtcCap (1<<10)
+#define NBCAP_CmpCap_SHIFT 12
+#define NBCAP_CmpCap_MASK 3
+#define NBCAP_MpCap_SHIFT 16
+#define NBCAP_MpCap_MASK 7
+#define NBCAP_MpCap_1N 7
+#define NBCAP_MpCap_2N 6
+#define NBCAP_MpCap_4N 5
+#define NBCAP_MpCap_8N 4
+#define NBCAP_MpCap_32N 0
+#define NBCAP_UnGangEn_SHIFT 20
+#define NBCAP_UnGangEn_MASK 0xf
+#define NBCAP_L3Cap (1<<25)
+#define NBCAP_HtAcCap (1<<26)
/* 04/04/2006 18:00 */
@@ -942,7 +942,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
#define NB_EXT_CONF 0x188
#define DOWNCORE_CTRL 0x190
-#define DWNCC_DisCore_SHIFT 0
+#define DWNCC_DisCore_SHIFT 0
#define DWNCC_DisCore_MASK 0xf
/* Function 5 for FBDIMM */
diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h
index cf449f7..12588a6 100644
--- a/src/northbridge/amd/amdht/AsPsDefs.h
+++ b/src/northbridge/amd/amdht/AsPsDefs.h
@@ -294,6 +294,6 @@
#define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT)
-#define WAIT_PSTATE_TIMEOUT 80000000 /* 0.1 s , unit : 1.25 ns */
+#define WAIT_PSTATE_TIMEOUT 80000000 /* 0.1 s , unit : 1.25 ns */
#endif
diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h
index bfeee0e..37cd102 100644
--- a/src/northbridge/amd/amdk8/f.h
+++ b/src/northbridge/amd/amdk8/f.h
@@ -4,41 +4,41 @@
/* Definitions of various K8 registers */
/* Function 0 */
#define HT_TRANSACTION_CONTROL 0x68
-#define HTTC_DIS_RD_B_P (1 << 0)
-#define HTTC_DIS_RD_DW_P (1 << 1)
-#define HTTC_DIS_WR_B_P (1 << 2)
-#define HTTC_DIS_WR_DW_P (1 << 3)
-#define HTTC_DIS_MTS (1 << 4)
-#define HTTC_CPU1_EN (1 << 5)
-#define HTTC_CPU_REQ_PASS_PW (1 << 6)
-#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
-#define HTTC_DIS_P_MEM_C (1 << 8)
-#define HTTC_DIS_RMT_MEM_C (1 << 9)
-#define HTTC_DIS_FILL_P (1 << 10)
-#define HTTC_RSP_PASS_PW (1 << 11)
-#define HTTC_CHG_ISOC_TO_ORD (1 << 12)
-#define HTTC_BUF_REL_PRI_SHIFT 13
-#define HTTC_BUF_REL_PRI_MASK 3
-#define HTTC_BUF_REL_PRI_64 0
-#define HTTC_BUF_REL_PRI_16 1
-#define HTTC_BUF_REL_PRI_8 2
-#define HTTC_BUF_REL_PRI_2 3
-#define HTTC_LIMIT_CLDT_CFG (1 << 15)
-#define HTTC_LINT_EN (1 << 16)
-#define HTTC_APIC_EXT_BRD_CST (1 << 17)
-#define HTTC_APIC_EXT_ID (1 << 18)
-#define HTTC_APIC_EXT_SPUR (1 << 19)
-#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
-#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
-#define HTTC_DS_NP_REQ_LIMIT_MASK 3
-#define HTTC_DS_NP_REQ_LIMIT_NONE 0
-#define HTTC_DS_NP_REQ_LIMIT_1 1
-#define HTTC_DS_NP_REQ_LIMIT_4 2
-#define HTTC_DS_NP_REQ_LIMIT_8 3
-#define HTTC_MED_PRI_BYP_CNT_SHIFT 24
-#define HTTC_MED_PRI_BYP_CNT_MASK 3
-#define HTTC_HI_PRI_BYP_CNT_SHIFT 26
-#define HTTC_HI_PRI_BYP_CNT_MASK 3
+#define HTTC_DIS_RD_B_P (1 << 0)
+#define HTTC_DIS_RD_DW_P (1 << 1)
+#define HTTC_DIS_WR_B_P (1 << 2)
+#define HTTC_DIS_WR_DW_P (1 << 3)
+#define HTTC_DIS_MTS (1 << 4)
+#define HTTC_CPU1_EN (1 << 5)
+#define HTTC_CPU_REQ_PASS_PW (1 << 6)
+#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
+#define HTTC_DIS_P_MEM_C (1 << 8)
+#define HTTC_DIS_RMT_MEM_C (1 << 9)
+#define HTTC_DIS_FILL_P (1 << 10)
+#define HTTC_RSP_PASS_PW (1 << 11)
+#define HTTC_CHG_ISOC_TO_ORD (1 << 12)
+#define HTTC_BUF_REL_PRI_SHIFT 13
+#define HTTC_BUF_REL_PRI_MASK 3
+#define HTTC_BUF_REL_PRI_64 0
+#define HTTC_BUF_REL_PRI_16 1
+#define HTTC_BUF_REL_PRI_8 2
+#define HTTC_BUF_REL_PRI_2 3
+#define HTTC_LIMIT_CLDT_CFG (1 << 15)
+#define HTTC_LINT_EN (1 << 16)
+#define HTTC_APIC_EXT_BRD_CST (1 << 17)
+#define HTTC_APIC_EXT_ID (1 << 18)
+#define HTTC_APIC_EXT_SPUR (1 << 19)
+#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
+#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
+#define HTTC_DS_NP_REQ_LIMIT_MASK 3
+#define HTTC_DS_NP_REQ_LIMIT_NONE 0
+#define HTTC_DS_NP_REQ_LIMIT_1 1
+#define HTTC_DS_NP_REQ_LIMIT_4 2
+#define HTTC_DS_NP_REQ_LIMIT_8 3
+#define HTTC_MED_PRI_BYP_CNT_SHIFT 24
+#define HTTC_MED_PRI_BYP_CNT_MASK 3
+#define HTTC_HI_PRI_BYP_CNT_SHIFT 26
+#define HTTC_HI_PRI_BYP_CNT_MASK 3
/* Function 1 */
@@ -56,33 +56,33 @@
#define DRAM_BANK_ADDR_MAP 0x80
#define DRAM_CTRL 0x78
-#define DC_RdPtrInit_SHIFT 0
-#define DC_RdPrtInit_MASK 0xf
-#define DC_RdPadRcvFifoDly_SHIFT 4
-#define DC_RdPadRcvFifoDly_MASK 7
-#define DC_RdPadRcvFiloDly_1_5_CLK 2
-#define DC_RdPadRcvFiloDly_2_CLK 3
-#define DC_RdPadRcvFiloDly_2_5_CLK 4
-#define DC_RdPadRcvFiloDly_3_CLK 5
-#define DC_RdPadRcvFiloDly_3_5_CLK 6
-#define DC_AltVidC3MemClkTriEn (1<<16)
-#define DC_DllTempAdjTime_SHIFT 17
-#define DC_DllTempAdjTime_MASK 1
-#define DC_DllTempAdjTime_5_MS 0
-#define DC_DllTempAdjTime_1_MS 1
-#define DC_DqsRcvEnTrain (1<<18)
+#define DC_RdPtrInit_SHIFT 0
+#define DC_RdPrtInit_MASK 0xf
+#define DC_RdPadRcvFifoDly_SHIFT 4
+#define DC_RdPadRcvFifoDly_MASK 7
+#define DC_RdPadRcvFiloDly_1_5_CLK 2
+#define DC_RdPadRcvFiloDly_2_CLK 3
+#define DC_RdPadRcvFiloDly_2_5_CLK 4
+#define DC_RdPadRcvFiloDly_3_CLK 5
+#define DC_RdPadRcvFiloDly_3_5_CLK 6
+#define DC_AltVidC3MemClkTriEn (1<<16)
+#define DC_DllTempAdjTime_SHIFT 17
+#define DC_DllTempAdjTime_MASK 1
+#define DC_DllTempAdjTime_5_MS 0
+#define DC_DllTempAdjTime_1_MS 1
+#define DC_DqsRcvEnTrain (1<<18)
#define DRAM_INIT 0x7c
-#define DI_MrsAddress_SHIFT 0
-#define DI_MrsAddress_MASK 0xffff
-#define DI_MrsBank_SHIFT 16
-#define DI_MrsBank_MASK 7
-#define DI_SendRchgAll (1<<24)
-#define DI_SendAutoRefresh (1<<25)
-#define DI_SendMrsCmd (1<<26)
-#define DI_DeassertMemRstX (1<<27)
-#define DI_AssertCke (1<<28)
-#define DI_EnDramInit (1<<31)
+#define DI_MrsAddress_SHIFT 0
+#define DI_MrsAddress_MASK 0xffff
+#define DI_MrsBank_SHIFT 16
+#define DI_MrsBank_MASK 7
+#define DI_SendRchgAll (1<<24)
+#define DI_SendAutoRefresh (1<<25)
+#define DI_SendMrsCmd (1<<26)
+#define DI_DeassertMemRstX (1<<27)
+#define DI_AssertCke (1<<28)
+#define DI_EnDramInit (1<<31)
#define DRAM_TIMING_LOW 0x88
#define DTL_TCL_SHIFT 0
@@ -94,17 +94,17 @@
#define DTL_TRCD_MASK 3
#define DTL_TRCD_BASE 3
#define DTL_TRCD_MIN 3
-#define DTL_TRCD_MAX 6
+#define DTL_TRCD_MAX 6
#define DTL_TRP_SHIFT 8
#define DTL_TRP_MASK 3
#define DTL_TRP_BASE 3
#define DTL_TRP_MIN 3
-#define DTL_TRP_MAX 6
+#define DTL_TRP_MAX 6
#define DTL_TRTP_SHIFT 11
#define DTL_TRTP_MASK 1
#define DTL_TRTP_BASE 2
#define DTL_TRTP_MIN 2 /* 4 for 64 bytes*/
-#define DTL_TRTP_MAX 3 /* 5 for 64 bytes */
+#define DTL_TRTP_MAX 3 /* 5 for 64 bytes */
#define DTL_TRAS_SHIFT 12
#define DTL_TRAS_MASK 0xf
#define DTL_TRAS_BASE 3
@@ -120,28 +120,28 @@
#define DTL_TWR_BASE 3
#define DTL_TWR_MIN 3
#define DTL_TWR_MAX 6
-#define DTL_TRRD_SHIFT 22
-#define DTL_TRRD_MASK 3
-#define DTL_TRRD_BASE 2
-#define DTL_TRRD_MIN 2
-#define DTL_TRRD_MAX 5
-#define DTL_MemClkDis_SHIFT 24 /* Channel A */
-#define DTL_MemClkDis3 (1 << 26)
-#define DTL_MemClkDis2 (1 << 27)
-#define DTL_MemClkDis1 (1 << 28)
-#define DTL_MemClkDis0 (1 << 29)
-#define DTL_MemClkDis1_AM2 (0x51 << 24)
-#define DTL_MemClkDis0_AM2 (0xa2 << 24)
-#define DTL_MemClkDis0_S1g1 (0xa2 << 24)
+#define DTL_TRRD_SHIFT 22
+#define DTL_TRRD_MASK 3
+#define DTL_TRRD_BASE 2
+#define DTL_TRRD_MIN 2
+#define DTL_TRRD_MAX 5
+#define DTL_MemClkDis_SHIFT 24 /* Channel A */
+#define DTL_MemClkDis3 (1 << 26)
+#define DTL_MemClkDis2 (1 << 27)
+#define DTL_MemClkDis1 (1 << 28)
+#define DTL_MemClkDis0 (1 << 29)
+#define DTL_MemClkDis1_AM2 (0x51 << 24)
+#define DTL_MemClkDis0_AM2 (0xa2 << 24)
+#define DTL_MemClkDis0_S1g1 (0xa2 << 24)
/* DTL_MemClkDis for m2 and s1g1 is different */
#define DRAM_TIMING_HIGH 0x8c
-#define DTH_TRWTTO_SHIFT 4
-#define DTH_TRWTTO_MASK 7
-#define DTH_TRWTTO_BASE 2
-#define DTH_TRWTTO_MIN 2
-#define DTH_TRWTTO_MAX 9
+#define DTH_TRWTTO_SHIFT 4
+#define DTH_TRWTTO_MASK 7
+#define DTH_TRWTTO_BASE 2
+#define DTH_TRWTTO_MIN 2
+#define DTH_TRWTTO_MAX 9
#define DTH_TWTR_SHIFT 8
#define DTH_TWTR_MASK 3
#define DTH_TWTR_BASE 0
@@ -152,210 +152,210 @@
#define DTH_TWRRD_BASE 0
#define DTH_TWRRD_MIN 0
#define DTH_TWRRD_MAX 3
-#define DTH_TWRWR_SHIFT 12
-#define DTH_TWRWR_MASK 3
-#define DTH_TWRWR_BASE 1
-#define DTH_TWRWR_MIN 1
-#define DTH_TWRWR_MAX 3
-#define DTH_TRDRD_SHIFT 14
-#define DTH_TRDRD_MASK 3
-#define DTH_TRDRD_BASE 2
-#define DTH_TRDRD_MIN 2
-#define DTH_TRDRD_MAX 5
+#define DTH_TWRWR_SHIFT 12
+#define DTH_TWRWR_MASK 3
+#define DTH_TWRWR_BASE 1
+#define DTH_TWRWR_MIN 1
+#define DTH_TWRWR_MAX 3
+#define DTH_TRDRD_SHIFT 14
+#define DTH_TRDRD_MASK 3
+#define DTH_TRDRD_BASE 2
+#define DTH_TRDRD_MIN 2
+#define DTH_TRDRD_MAX 5
#define DTH_TREF_SHIFT 16
#define DTH_TREF_MASK 3
#define DTH_TREF_7_8_US 2
#define DTH_TREF_3_9_US 3
-#define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */
-#define DTH_TRFC_MASK 7
+#define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */
+#define DTH_TRFC_MASK 7
#define DTH_TRFC_75_256M 0
#define DTH_TRFC_105_512M 1
-#define DTH_TRFC_127_5_1G 2
-#define DTH_TRFC_195_2G 3
-#define DTH_TRFC_327_5_4G 4
-#define DTH_TRFC1_SHIFT 23 /*for Logical DIMM1 */
-#define DTH_TRFC2_SHIFT 26 /*for Logical DIMM2 */
-#define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */
+#define DTH_TRFC_127_5_1G 2
+#define DTH_TRFC_195_2G 3
+#define DTH_TRFC_327_5_4G 4
+#define DTH_TRFC1_SHIFT 23 /*for Logical DIMM1 */
+#define DTH_TRFC2_SHIFT 26 /*for Logical DIMM2 */
+#define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */
#define DRAM_CONFIG_LOW 0x90
#define DCL_InitDram (1<<0)
#define DCL_ExitSelfRef (1<<1)
-#define DCL_DramTerm_SHIFT 4
-#define DCL_DramTerm_MASK 3
-#define DCL_DramTerm_No 0
-#define DCL_DramTerm_75_OH 1
-#define DCL_DramTerm_150_OH 2
-#define DCL_DramTerm_50_OH 3
-#define DCL_DrvWeak (1<<7)
-#define DCL_ParEn (1<<8)
-#define DCL_SelfRefRateEn (1<<9)
-#define DCL_BurstLength32 (1<<10)
-#define DCL_Width128 (1<<11)
-#define DCL_X4Dimm_SHIFT 12
-#define DCL_X4Dimm_MASK 0xf
-#define DCL_UnBuffDimm (1<<16)
+#define DCL_DramTerm_SHIFT 4
+#define DCL_DramTerm_MASK 3
+#define DCL_DramTerm_No 0
+#define DCL_DramTerm_75_OH 1
+#define DCL_DramTerm_150_OH 2
+#define DCL_DramTerm_50_OH 3
+#define DCL_DrvWeak (1<<7)
+#define DCL_ParEn (1<<8)
+#define DCL_SelfRefRateEn (1<<9)
+#define DCL_BurstLength32 (1<<10)
+#define DCL_Width128 (1<<11)
+#define DCL_X4Dimm_SHIFT 12
+#define DCL_X4Dimm_MASK 0xf
+#define DCL_UnBuffDimm (1<<16)
#define DCL_DimmEccEn (1<<19)
#define DRAM_CONFIG_HIGH 0x94
-#define DCH_MemClkFreq_SHIFT 0
-#define DCH_MemClkFreq_MASK 7
-#define DCH_MemClkFreq_200MHz 0
-#define DCH_MemClkFreq_266MHz 1
-#define DCH_MemClkFreq_333MHz 2
+#define DCH_MemClkFreq_SHIFT 0
+#define DCH_MemClkFreq_MASK 7
+#define DCH_MemClkFreq_200MHz 0
+#define DCH_MemClkFreq_266MHz 1
+#define DCH_MemClkFreq_333MHz 2
#define DCH_MemClkFreq_400MHz 3
-#define DCH_MemClkFreqVal (1<<3)
+#define DCH_MemClkFreqVal (1<<3)
#define DCH_MaxAsyncLat_SHIFT 4
#define DCH_MaxAsyncLat_MASK 0xf
#define DCH_MaxAsyncLat_BASE 0
#define DCH_MaxAsyncLat_MIN 0
#define DCH_MaxAsyncLat_MAX 15
-#define DCH_RDqsEn (1<<12)
-#define DCH_DisDramInterface (1<<14)
-#define DCH_PowerDownEn (1<<15)
-#define DCH_PowerDownMode_SHIFT 16
-#define DCH_PowerDownMode_MASK 1
-#define DCH_PowerDownMode_Channel_CKE 0
-#define DCH_PowerDownMode_ChipSelect_CKE 1
-#define DCH_FourRankSODimm (1<<17)
-#define DCH_FourRankRDimm (1<<18)
-#define DCH_SlowAccessMode (1<<19)
-#define DCH_BankSwizzleMode (1<<22)
-#define DCH_DcqBypassMax_SHIFT 24
-#define DCH_DcqBypassMax_MASK 0xf
-#define DCH_DcqBypassMax_BASE 0
-#define DCH_DcqBypassMax_MIN 0
-#define DCH_DcqBypassMax_MAX 15
-#define DCH_FourActWindow_SHIFT 28
-#define DCH_FourActWindow_MASK 0xf
-#define DCH_FourActWindow_BASE 7
-#define DCH_FourActWindow_MIN 8
-#define DCH_FourActWindow_MAX 20
+#define DCH_RDqsEn (1<<12)
+#define DCH_DisDramInterface (1<<14)
+#define DCH_PowerDownEn (1<<15)
+#define DCH_PowerDownMode_SHIFT 16
+#define DCH_PowerDownMode_MASK 1
+#define DCH_PowerDownMode_Channel_CKE 0
+#define DCH_PowerDownMode_ChipSelect_CKE 1
+#define DCH_FourRankSODimm (1<<17)
+#define DCH_FourRankRDimm (1<<18)
+#define DCH_SlowAccessMode (1<<19)
+#define DCH_BankSwizzleMode (1<<22)
+#define DCH_DcqBypassMax_SHIFT 24
+#define DCH_DcqBypassMax_MASK 0xf
+#define DCH_DcqBypassMax_BASE 0
+#define DCH_DcqBypassMax_MIN 0
+#define DCH_DcqBypassMax_MAX 15
+#define DCH_FourActWindow_SHIFT 28
+#define DCH_FourActWindow_MASK 0xf
+#define DCH_FourActWindow_BASE 7
+#define DCH_FourActWindow_MIN 8
+#define DCH_FourActWindow_MAX 20
// for 0x98 index and 0x9c data
#define DRAM_CTRL_ADDI_DATA_OFFSET 0x98
-#define DCAO_DctOffset_SHIFT 0
-#define DCAO_DctOffset_MASK 0x3fffffff
-#define DCAO_DctAccessWrite (1<<30)
-#define DCAO_DctAccessDone (1<<31)
+#define DCAO_DctOffset_SHIFT 0
+#define DCAO_DctOffset_MASK 0x3fffffff
+#define DCAO_DctAccessWrite (1<<30)
+#define DCAO_DctAccessDone (1<<31)
#define DRAM_CTRL_ADDI_DATA_PORT 0x9c
#define DRAM_OUTPUT_DRV_COMP_CTRL 0x00
-#define DODCC_CkeDrvStren_SHIFT 0
-#define DODCC_CkeDrvStren_MASK 3
-#define DODCC_CkeDrvStren_1_0X 0
-#define DODCC_CkeDrvStren_1_25X 1
-#define DODCC_CkeDrvStren_1_5X 2
-#define DODCC_CkeDrvStren_2_0X 3
-#define DODCC_CsOdtDrvStren_SHIFT 4
-#define DODCC_CsOdtDrvStren_MASK 3
-#define DODCC_CsOdtDrvStren_1_0X 0
-#define DODCC_CsOdtDrvStren_1_25X 1
-#define DODCC_CsOdtDrvStren_1_5X 2
-#define DODCC_CsOdtDrvStren_2_0X 3
-#define DODCC_AddrCmdDrvStren_SHIFT 8
-#define DODCC_AddrCmdDrvStren_MASK 3
-#define DODCC_AddrCmdDrvStren_1_0X 0
-#define DODCC_AddrCmdDrvStren_1_25X 1
-#define DODCC_AddrCmdDrvStren_1_5X 2
-#define DODCC_AddrCmdDrvStren_2_0X 3
-#define DODCC_ClkDrvStren_SHIFT 12
-#define DODCC_ClkDrvStren_MASK 3
-#define DODCC_ClkDrvStren_0_75X 0
-#define DODCC_ClkDrvStren_1_0X 1
-#define DODCC_ClkDrvStren_1_25X 2
-#define DODCC_ClkDrvStren_1_5X 3
-#define DODCC_DataDrvStren_SHIFT 16
-#define DODCC_DataDrvStren_MASK 3
-#define DODCC_DataDrvStren_0_75X 0
-#define DODCC_DataDrvStren_1_0X 1
-#define DODCC_DataDrvStren_1_25X 2
-#define DODCC_DataDrvStren_1_5X 3
-#define DODCC_DqsDrvStren_SHIFT 20
-#define DODCC_DqsDrvStren_MASK 3
-#define DODCC_DqsDrvStren_0_75X 0
-#define DODCC_DqsDrvStren_1_0X 1
-#define DODCC_DqsDrvStren_1_25X 2
-#define DODCC_DqsDrvStren_1_5X 3
-#define DODCC_ProcOdt_SHIFT 28
-#define DODCC_ProcOdt_MASK 3
-#define DODCC_ProcOdt_300_OHMS 0
-#define DODCC_ProcOdt_150_OHMS 1
-#define DODCC_ProcOdt_75_OHMS 2
+#define DODCC_CkeDrvStren_SHIFT 0
+#define DODCC_CkeDrvStren_MASK 3
+#define DODCC_CkeDrvStren_1_0X 0
+#define DODCC_CkeDrvStren_1_25X 1
+#define DODCC_CkeDrvStren_1_5X 2
+#define DODCC_CkeDrvStren_2_0X 3
+#define DODCC_CsOdtDrvStren_SHIFT 4
+#define DODCC_CsOdtDrvStren_MASK 3
+#define DODCC_CsOdtDrvStren_1_0X 0
+#define DODCC_CsOdtDrvStren_1_25X 1
+#define DODCC_CsOdtDrvStren_1_5X 2
+#define DODCC_CsOdtDrvStren_2_0X 3
+#define DODCC_AddrCmdDrvStren_SHIFT 8
+#define DODCC_AddrCmdDrvStren_MASK 3
+#define DODCC_AddrCmdDrvStren_1_0X 0
+#define DODCC_AddrCmdDrvStren_1_25X 1
+#define DODCC_AddrCmdDrvStren_1_5X 2
+#define DODCC_AddrCmdDrvStren_2_0X 3
+#define DODCC_ClkDrvStren_SHIFT 12
+#define DODCC_ClkDrvStren_MASK 3
+#define DODCC_ClkDrvStren_0_75X 0
+#define DODCC_ClkDrvStren_1_0X 1
+#define DODCC_ClkDrvStren_1_25X 2
+#define DODCC_ClkDrvStren_1_5X 3
+#define DODCC_DataDrvStren_SHIFT 16
+#define DODCC_DataDrvStren_MASK 3
+#define DODCC_DataDrvStren_0_75X 0
+#define DODCC_DataDrvStren_1_0X 1
+#define DODCC_DataDrvStren_1_25X 2
+#define DODCC_DataDrvStren_1_5X 3
+#define DODCC_DqsDrvStren_SHIFT 20
+#define DODCC_DqsDrvStren_MASK 3
+#define DODCC_DqsDrvStren_0_75X 0
+#define DODCC_DqsDrvStren_1_0X 1
+#define DODCC_DqsDrvStren_1_25X 2
+#define DODCC_DqsDrvStren_1_5X 3
+#define DODCC_ProcOdt_SHIFT 28
+#define DODCC_ProcOdt_MASK 3
+#define DODCC_ProcOdt_300_OHMS 0
+#define DODCC_ProcOdt_150_OHMS 1
+#define DODCC_ProcOdt_75_OHMS 2
#define DRAM_WRITE_DATA_TIMING_CTRL_LOW 0x01
-#define DWDTCL_WrDatTimeByte0_SHIFT 0
-#define DWDTC_WrDatTimeByte_MASK 0x3f
-#define DWDTC_WrDatTimeByte_BASE 0
-#define DWDTC_WrDatTimeByte_MIN 0
-#define DWDTC_WrDatTimeByte_MAX 47
-#define DWDTCL_WrDatTimeByte1_SHIFT 8
-#define DWDTCL_WrDatTimeByte2_SHIFT 16
-#define DWDTCL_WrDatTimeByte3_SHIFT 24
+#define DWDTCL_WrDatTimeByte0_SHIFT 0
+#define DWDTC_WrDatTimeByte_MASK 0x3f
+#define DWDTC_WrDatTimeByte_BASE 0
+#define DWDTC_WrDatTimeByte_MIN 0
+#define DWDTC_WrDatTimeByte_MAX 47
+#define DWDTCL_WrDatTimeByte1_SHIFT 8
+#define DWDTCL_WrDatTimeByte2_SHIFT 16
+#define DWDTCL_WrDatTimeByte3_SHIFT 24
#define DRAM_WRITE_DATA_TIMING_CTRL_HIGH 0x02
-#define DWDTCH_WrDatTimeByte4_SHIFT 0
-#define DWDTCH_WrDatTimeByte5_SHIFT 8
-#define DWDTCH_WrDatTimeByte6_SHIFT 16
-#define DWDTCH_WrDatTimeByte7_SHIFT 24
+#define DWDTCH_WrDatTimeByte4_SHIFT 0
+#define DWDTCH_WrDatTimeByte5_SHIFT 8
+#define DWDTCH_WrDatTimeByte6_SHIFT 16
+#define DWDTCH_WrDatTimeByte7_SHIFT 24
#define DRAM_WRITE_DATA_ECC_TIMING_CTRL 0x03
-#define DWDETC_WrChkTime_SHIFT 0
-#define DWDETC_WrChkTime_MASK 0x3f
-#define DWDETC_WrChkTime_BASE 0
-#define DWDETC_WrChkTime_MIN 0
-#define DWDETC_WrChkTime_MAX 47
+#define DWDETC_WrChkTime_SHIFT 0
+#define DWDETC_WrChkTime_MASK 0x3f
+#define DWDETC_WrChkTime_BASE 0
+#define DWDETC_WrChkTime_MIN 0
+#define DWDETC_WrChkTime_MAX 47
#define DRAM_ADDR_TIMING_CTRL 0x04
-#define DATC_CkeFineDelay_SHIFT 0
-#define DATC_CkeFineDelay_MASK 0x1f
-#define DATC_CkeFineDelay_BASE 0
-#define DATC_CkeFineDelay_MIN 0
-#define DATC_CkeFineDelay_MAX 31
-#define DATC_CkeSetup (1<<5)
-#define DATC_CsOdtFineDelay_SHIFT 8
-#define DATC_CsOdtFineDelay_MASK 0x1f
-#define DATC_CsOdtFineDelay_BASE 0
-#define DATC_CsOdtFineDelay_MIN 0
-#define DATC_CsOdtFineDelay_MAX 31
-#define DATC_CsOdtSetup (1<<13)
-#define DATC_AddrCmdFineDelay_SHIFT 16
-#define DATC_AddrCmdFineDelay_MASK 0x1f
-#define DATC_AddrCmdFineDelay_BASE 0
-#define DATC_AddrCmdFineDelay_MIN 0
-#define DATC_AddrCmdFineDelay_MAX 31
-#define DATC_AddrCmdSetup (1<<21)
+#define DATC_CkeFineDelay_SHIFT 0
+#define DATC_CkeFineDelay_MASK 0x1f
+#define DATC_CkeFineDelay_BASE 0
+#define DATC_CkeFineDelay_MIN 0
+#define DATC_CkeFineDelay_MAX 31
+#define DATC_CkeSetup (1<<5)
+#define DATC_CsOdtFineDelay_SHIFT 8
+#define DATC_CsOdtFineDelay_MASK 0x1f
+#define DATC_CsOdtFineDelay_BASE 0
+#define DATC_CsOdtFineDelay_MIN 0
+#define DATC_CsOdtFineDelay_MAX 31
+#define DATC_CsOdtSetup (1<<13)
+#define DATC_AddrCmdFineDelay_SHIFT 16
+#define DATC_AddrCmdFineDelay_MASK 0x1f
+#define DATC_AddrCmdFineDelay_BASE 0
+#define DATC_AddrCmdFineDelay_MIN 0
+#define DATC_AddrCmdFineDelay_MAX 31
+#define DATC_AddrCmdSetup (1<<21)
#define DRAM_READ_DQS_TIMING_CTRL_LOW 0x05
-#define DRDTCL_RdDqsTimeByte0_SHIFT 0
-#define DRDTC_RdDqsTimeByte_MASK 0x3f
-#define DRDTC_RdDqsTimeByte_BASE 0
-#define DRDTC_RdDqsTimeByte_MIN 0
-#define DRDTC_RdDqsTimeByte_MAX 47
-#define DRDTCL_RdDqsTimeByte1_SHIFT 8
-#define DRDTCL_RdDqsTimeByte2_SHIFT 16
-#define DRDTCL_RdDqsTimeByte3_SHIFT 24
+#define DRDTCL_RdDqsTimeByte0_SHIFT 0
+#define DRDTC_RdDqsTimeByte_MASK 0x3f
+#define DRDTC_RdDqsTimeByte_BASE 0
+#define DRDTC_RdDqsTimeByte_MIN 0
+#define DRDTC_RdDqsTimeByte_MAX 47
+#define DRDTCL_RdDqsTimeByte1_SHIFT 8
+#define DRDTCL_RdDqsTimeByte2_SHIFT 16
+#define DRDTCL_RdDqsTimeByte3_SHIFT 24
#define DRAM_READ_DQS_TIMING_CTRL_HIGH 0x06
-#define DRDTCH_RdDqsTimeByte4_SHIFT 0
-#define DRDTCH_RdDqsTimeByte5_SHIFT 8
-#define DRDTCH_RdDqsTimeByte6_SHIFT 16
-#define DRDTCH_RdDqsTimeByte7_SHIFT 24
+#define DRDTCH_RdDqsTimeByte4_SHIFT 0
+#define DRDTCH_RdDqsTimeByte5_SHIFT 8
+#define DRDTCH_RdDqsTimeByte6_SHIFT 16
+#define DRDTCH_RdDqsTimeByte7_SHIFT 24
#define DRAM_READ_DQS_ECC_TIMING_CTRL 0x07
-#define DRDETC_RdDqsTimeCheck_SHIFT 0
-#define DRDETC_RdDqsTimeCheck_MASK 0x3f
-#define DRDETC_RdDqsTimeCheck_BASE 0
-#define DRDETC_RdDqsTimeCheck_MIN 0
-#define DRDETC_RdDqsTimeCheck_MAX 47
+#define DRDETC_RdDqsTimeCheck_SHIFT 0
+#define DRDETC_RdDqsTimeCheck_MASK 0x3f
+#define DRDETC_RdDqsTimeCheck_BASE 0
+#define DRDETC_RdDqsTimeCheck_MIN 0
+#define DRDETC_RdDqsTimeCheck_MAX 47
#define DRAM_DQS_RECV_ENABLE_TIME0 0x10
-#define DDRET_DqsRcvEnDelay_SHIFT 0
-#define DDRET_DqsRcvEnDelay_MASK 0xff
-#define DDRET_DqsRcvEnDelay_BASE 0
-#define DDRET_DqsRcvEnDelay_MIN 0
-#define DDRET_DqsRcvEnDelay_MAX 0xae /* unit is 50ps */
+#define DDRET_DqsRcvEnDelay_SHIFT 0
+#define DDRET_DqsRcvEnDelay_MASK 0xff
+#define DDRET_DqsRcvEnDelay_BASE 0
+#define DDRET_DqsRcvEnDelay_MIN 0
+#define DDRET_DqsRcvEnDelay_MAX 0xae /* unit is 50ps */
#define DRAM_DQS_RECV_ENABLE_TIME1 0x13
#define DRAM_DQS_RECV_ENABLE_TIME2 0x16
@@ -365,38 +365,38 @@
that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10, 0x13, 0x16, 0x19
*/
#define DRAM_CTRL_MISC 0xa0
-#define DCM_MemClrStatus (1<<0)
-#define DCM_DisableJitter (1<<1)
-#define DCM_RdWrQByp_SHIFT 2
-#define DCM_RdWrQByp_MASK 3
-#define DCM_RdWrQByp_2 0
-#define DCM_RdWrQByp_4 1
-#define DCM_RdWrQByp_8 2
-#define DCM_RdWrQByp_16 3
-#define DCM_Mode64BitMux (1<<4)
-#define DCM_DCC_EN (1<<5)
-#define DCM_ILD_lmt_SHIFT 6
-#define DCM_ILD_lmt_MASK 7
-#define DCM_ILD_lmt_0 0
-#define DCM_ILD_lmt_4 1
-#define DCM_ILD_lmt_8 2
-#define DCM_ILD_lmt_16 3
-#define DCM_ILD_lmt_32 4
-#define DCM_ILD_lmt_64 5
-#define DCM_ILD_lmt_128 6
-#define DCM_ILD_lmt_256 7
-#define DCM_DramEnabled (1<<9)
-#define DCM_MemClkDis_SHIFT 24 /* Channel B */
-#define DCM_MemClkDis3 (1 << 26)
-#define DCM_MemClkDis2 (1 << 27)
-#define DCM_MemClkDis1 (1 << 28)
-#define DCM_MemClkDis0 (1 << 29)
+#define DCM_MemClrStatus (1<<0)
+#define DCM_DisableJitter (1<<1)
+#define DCM_RdWrQByp_SHIFT 2
+#define DCM_RdWrQByp_MASK 3
+#define DCM_RdWrQByp_2 0
+#define DCM_RdWrQByp_4 1
+#define DCM_RdWrQByp_8 2
+#define DCM_RdWrQByp_16 3
+#define DCM_Mode64BitMux (1<<4)
+#define DCM_DCC_EN (1<<5)
+#define DCM_ILD_lmt_SHIFT 6
+#define DCM_ILD_lmt_MASK 7
+#define DCM_ILD_lmt_0 0
+#define DCM_ILD_lmt_4 1
+#define DCM_ILD_lmt_8 2
+#define DCM_ILD_lmt_16 3
+#define DCM_ILD_lmt_32 4
+#define DCM_ILD_lmt_64 5
+#define DCM_ILD_lmt_128 6
+#define DCM_ILD_lmt_256 7
+#define DCM_DramEnabled (1<<9)
+#define DCM_MemClkDis_SHIFT 24 /* Channel B */
+#define DCM_MemClkDis3 (1 << 26)
+#define DCM_MemClkDis2 (1 << 27)
+#define DCM_MemClkDis1 (1 << 28)
+#define DCM_MemClkDis0 (1 << 29)
/* Function 3 */
#define MCA_NB_CONFIG 0x44
-#define MNC_ECC_EN (1 << 22)
-#define MNC_CHIPKILL_EN (1 << 23)
+#define MNC_ECC_EN (1 << 22)
+#define MNC_CHIPKILL_EN (1 << 23)
#define SCRUB_CONTROL 0x58
#define SCRUB_NONE 0
@@ -446,9 +446,9 @@ that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10,
#define NBCAP_MEMCLK_333MHZ 1
#define NBCAP_MEMCLK_NOLIMIT 0
#define NBCAP_MEMCTRL (1 << 8)
-#define NBCAP_HtcCap (1<<10)
-#define NBCAP_CmpCap_SHIFT 12
-#define NBCAP_CmpCap_MASK 3
+#define NBCAP_HtcCap (1<<10)
+#define NBCAP_CmpCap_SHIFT 12
+#define NBCAP_CmpCap_MASK 3
#define LinkConnected (1 << 0)
diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h
index 0e0f9f4..999bdde 100644
--- a/src/northbridge/amd/amdk8/pre_f.h
+++ b/src/northbridge/amd/amdk8/pre_f.h
@@ -4,41 +4,41 @@
/* Definitions of various K8 registers */
/* Function 0 */
#define HT_TRANSACTION_CONTROL 0x68
-#define HTTC_DIS_RD_B_P (1 << 0)
-#define HTTC_DIS_RD_DW_P (1 << 1)
-#define HTTC_DIS_WR_B_P (1 << 2)
-#define HTTC_DIS_WR_DW_P (1 << 3)
-#define HTTC_DIS_MTS (1 << 4)
-#define HTTC_CPU1_EN (1 << 5)
-#define HTTC_CPU_REQ_PASS_PW (1 << 6)
-#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
-#define HTTC_DIS_P_MEM_C (1 << 8)
-#define HTTC_DIS_RMT_MEM_C (1 << 9)
-#define HTTC_DIS_FILL_P (1 << 10)
-#define HTTC_RSP_PASS_PW (1 << 11)
-#define HTTC_CHG_ISOC_TO_ORD (1 << 12)
-#define HTTC_BUF_REL_PRI_SHIFT 13
-#define HTTC_BUF_REL_PRI_MASK 3
-#define HTTC_BUF_REL_PRI_64 0
-#define HTTC_BUF_REL_PRI_16 1
-#define HTTC_BUF_REL_PRI_8 2
-#define HTTC_BUF_REL_PRI_2 3
-#define HTTC_LIMIT_CLDT_CFG (1 << 15)
-#define HTTC_LINT_EN (1 << 16)
-#define HTTC_APIC_EXT_BRD_CST (1 << 17)
-#define HTTC_APIC_EXT_ID (1 << 18)
-#define HTTC_APIC_EXT_SPUR (1 << 19)
-#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
-#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
-#define HTTC_DS_NP_REQ_LIMIT_MASK 3
-#define HTTC_DS_NP_REQ_LIMIT_NONE 0
-#define HTTC_DS_NP_REQ_LIMIT_1 1
-#define HTTC_DS_NP_REQ_LIMIT_4 2
-#define HTTC_DS_NP_REQ_LIMIT_8 3
-#define HTTC_MED_PRI_BYP_CNT_SHIFT 24
-#define HTTC_MED_PRI_BYP_CNT_MASK 3
-#define HTTC_HI_PRI_BYP_CNT_SHIFT 26
-#define HTTC_HI_PRI_BYP_CNT_MASK 3
+#define HTTC_DIS_RD_B_P (1 << 0)
+#define HTTC_DIS_RD_DW_P (1 << 1)
+#define HTTC_DIS_WR_B_P (1 << 2)
+#define HTTC_DIS_WR_DW_P (1 << 3)
+#define HTTC_DIS_MTS (1 << 4)
+#define HTTC_CPU1_EN (1 << 5)
+#define HTTC_CPU_REQ_PASS_PW (1 << 6)
+#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
+#define HTTC_DIS_P_MEM_C (1 << 8)
+#define HTTC_DIS_RMT_MEM_C (1 << 9)
+#define HTTC_DIS_FILL_P (1 << 10)
+#define HTTC_RSP_PASS_PW (1 << 11)
+#define HTTC_CHG_ISOC_TO_ORD (1 << 12)
+#define HTTC_BUF_REL_PRI_SHIFT 13
+#define HTTC_BUF_REL_PRI_MASK 3
+#define HTTC_BUF_REL_PRI_64 0
+#define HTTC_BUF_REL_PRI_16 1
+#define HTTC_BUF_REL_PRI_8 2
+#define HTTC_BUF_REL_PRI_2 3
+#define HTTC_LIMIT_CLDT_CFG (1 << 15)
+#define HTTC_LINT_EN (1 << 16)
+#define HTTC_APIC_EXT_BRD_CST (1 << 17)
+#define HTTC_APIC_EXT_ID (1 << 18)
+#define HTTC_APIC_EXT_SPUR (1 << 19)
+#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
+#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
+#define HTTC_DS_NP_REQ_LIMIT_MASK 3
+#define HTTC_DS_NP_REQ_LIMIT_NONE 0
+#define HTTC_DS_NP_REQ_LIMIT_1 1
+#define HTTC_DS_NP_REQ_LIMIT_4 2
+#define HTTC_DS_NP_REQ_LIMIT_8 3
+#define HTTC_MED_PRI_BYP_CNT_SHIFT 24
+#define HTTC_MED_PRI_BYP_CNT_MASK 3
+#define HTTC_HI_PRI_BYP_CNT_SHIFT 26
+#define HTTC_HI_PRI_BYP_CNT_MASK 3
/* Function 1 */
@@ -182,8 +182,8 @@
/* Function 3 */
#define MCA_NB_CONFIG 0x44
-#define MNC_ECC_EN (1 << 22)
-#define MNC_CHIPKILL_EN (1 << 23)
+#define MNC_ECC_EN (1 << 22)
+#define MNC_CHIPKILL_EN (1 << 23)
#define SCRUB_CONTROL 0x58
#define SCRUB_NONE 0
#define SCRUB_40ns 1
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h
index a92fdb8..c0714ae 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti.h
+++ b/src/northbridge/amd/amdmct/wrappers/mcti.h
@@ -29,17 +29,17 @@
/*----------------------------------------------------------------------------
COMMENT OUT ALL BUT 1
----------------------------------------------------------------------------*/
-//#define BUILD_VERSION REV_F /*BIOS supports rev F only*/
-//#define BUILD_VERSION REV_DR /*BIOS supports rev 10 only*/
-//#define BUILD_VERSION REV_FDR /*BIOS supports both rev F and 10*/
+//#define BUILD_VERSION REV_F /*BIOS supports rev F only*/
+//#define BUILD_VERSION REV_DR /*BIOS supports rev 10 only*/
+//#define BUILD_VERSION REV_FDR /*BIOS supports both rev F and 10*/
/*----------------------------------------------------------------------------
COMMENT OUT ALL BUT 1
----------------------------------------------------------------------------*/
#ifndef SYSTEM_TYPE
-#define SYSTEM_TYPE SERVER
-//#define SYSTEM_TYPE DESKTOP
-//#define SYSTEM_TYPE MOBILE
+#define SYSTEM_TYPE SERVER
+//#define SYSTEM_TYPE DESKTOP
+//#define SYSTEM_TYPE MOBILE
#endif
/*----------------------------------------------------------------------------
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