[coreboot-gerrit] New patch to review for coreboot: aa92964 southbridge/intel/sch: Remove a trailing whitespace

[HAOUAS Elyes (ehaouas@noos.fr)]

HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6337

-gerrit

commit aa929643a21d85daf13ea6a092d7fba3adbe2848
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Tue Jul 22 19:27:02 2014 +0200

    southbridge/intel/sch: Remove a trailing whitespace
    
    Change-Id: Ia67a4348ec540010d5c2db19657eb244fc5d763a
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 src/southbridge/intel/sch/smi.c        | 38 +++++++++++++++++-----------------
 src/southbridge/intel/sch/smihandler.c | 38 +++++++++++++++++-----------------
 2 files changed, 38 insertions(+), 38 deletions(-)

diff --git a/src/southbridge/intel/sch/smi.c b/src/southbridge/intel/sch/smi.c
index 08733a7..9d72039 100644
--- a/src/southbridge/intel/sch/smi.c
+++ b/src/southbridge/intel/sch/smi.c
@@ -33,11 +33,11 @@ extern unsigned char _binary_smm_size;
 
 /* I945 */
 #define SMRAM		0x9d
-#define   D_OPEN	(1 << 6)
-#define   D_CLS		(1 << 5)
-#define   D_LCK		(1 << 4)
-#define   G_SMRAME	(1 << 3)
-#define   C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
+#define D_OPEN	(1 << 6)
+#define D_CLS		(1 << 5)
+#define D_LCK		(1 << 4)
+#define G_SMRAME	(1 << 3)
+#define C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
 
 /* ICH7 */
 #define PM1_STS		0x00
@@ -52,20 +52,20 @@ extern unsigned char _binary_smm_size;
 #define GPE0_STS	0x28
 #define GPE0_EN		0x2c
 #define SMI_EN		0x30
-#define   EL_SMI_EN	 (1 << 25) // Intel Quick Resume Technology
-#define   INTEL_USB2_EN	 (1 << 18) // Intel-Specific USB2 SMI logic
-#define   LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
-#define   PERIODIC_EN	 (1 << 14) // SMI on PERIODIC_STS in SMI_STS
-#define   TCO_EN	 (1 << 13) // Enable TCO Logic (BIOSWE et al)
-#define   MCSMI_EN	 (1 << 11) // Trap microcontroller range access
-#define   BIOS_RLS	 (1 <<  7) // asserts SCI on bit set
-#define   SWSMI_TMR_EN	 (1 <<  6) // start software smi timer on bit set
-#define   APMC_EN	 (1 <<  5) // Writes to APM_CNT cause SMI#
-#define   SLP_SMI_EN	 (1 <<  4) // Write to SLP_EN in PM1_CNT asserts SMI#
-#define   LEGACY_USB_EN  (1 <<  3) // Legacy USB circuit SMI logic
-#define   BIOS_EN	 (1 <<  2) // Assert SMI# on setting GBL_RLS bit
-#define   EOS		 (1 <<  1) // End of SMI (deassert SMI#)
-#define   GBL_SMI_EN	 (1 <<  0) // SMI# generation at all?
+#define EL_SMI_EN	 (1 << 25) // Intel Quick Resume Technology
+#define INTEL_USB2_EN	 (1 << 18) // Intel-Specific USB2 SMI logic
+#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
+#define PERIODIC_EN	 (1 << 14) // SMI on PERIODIC_STS in SMI_STS
+#define TCO_EN	 (1 << 13) // Enable TCO Logic (BIOSWE et al)
+#define MCSMI_EN	 (1 << 11) // Trap microcontroller range access
+#define BIOS_RLS	 (1 <<  7) // asserts SCI on bit set
+#define SWSMI_TMR_EN	 (1 <<  6) // start software smi timer on bit set
+#define APMC_EN	 (1 <<  5) // Writes to APM_CNT cause SMI#
+#define SLP_SMI_EN	 (1 <<  4) // Write to SLP_EN in PM1_CNT asserts SMI#
+#define LEGACY_USB_EN  (1 <<  3) // Legacy USB circuit SMI logic
+#define BIOS_EN	 (1 <<  2) // Assert SMI# on setting GBL_RLS bit
+#define EOS		 (1 <<  1) // End of SMI (deassert SMI#)
+#define GBL_SMI_EN	 (1 <<  0) // SMI# generation at all?
 #define SMI_STS		0x34
 #define ALT_GP_SMI_EN	0x38
 #define ALT_GP_SMI_STS	0x3a
diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c
index 5074138..5286e89 100644
--- a/src/southbridge/intel/sch/smihandler.c
+++ b/src/southbridge/intel/sch/smihandler.c
@@ -29,11 +29,11 @@
 
 /* I945 */
 #define SMRAM		0x9d
-#define   D_OPEN	(1 << 6)
-#define   D_CLS		(1 << 5)
-#define   D_LCK		(1 << 4)
-#define   G_SMRANE	(1 << 3)
-#define   C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
+#define D_OPEN	(1 << 6)
+#define D_CLS		(1 << 5)
+#define D_LCK		(1 << 4)
+#define G_SMRANE	(1 << 3)
+#define C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
 
 /* ICH7 */
 #define PM1_STS		0x00
@@ -48,20 +48,20 @@
 #define GPE0_STS	0x28
 #define GPE0_EN		0x2c
 #define SMI_EN		0x30
-#define   EL_SMI_EN	 (1 << 25) // Intel Quick Resume Technology
-#define   INTEL_USB2_EN	 (1 << 18) // Intel-Specific USB2 SMI logic
-#define   LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
-#define   PERIODIC_EN	 (1 << 14) // SMI on PERIODIC_STS in SMI_STS
-#define   TCO_EN	 (1 << 13) // Enable TCO Logic (BIOSWE et al)
-#define   MCSMI_EN	 (1 << 11) // Trap microcontroller range access
-#define   BIOS_RLS	 (1 <<  7) // asserts SCI on bit set
-#define   SWSMI_TMR_EN	 (1 <<  6) // start software smi timer on bit set
-#define   APMC_EN	 (1 <<  5) // Writes to APM_CNT cause SMI#
-#define   SLP_SMI_EN	 (1 <<  4) // Write to SLP_EN in PM1_CNT asserts SMI#
-#define   LEGACY_USB_EN  (1 <<  3) // Legacy USB circuit SMI logic
-#define   BIOS_EN	 (1 <<  2) // Assert SMI# on setting GBL_RLS bit
-#define   EOS		 (1 <<  1) // End of SMI (deassert SMI#)
-#define   GBL_SMI_EN	 (1 <<  0) // SMI# generation at all?
+#define EL_SMI_EN	 (1 << 25) // Intel Quick Resume Technology
+#define INTEL_USB2_EN	 (1 << 18) // Intel-Specific USB2 SMI logic
+#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
+#define PERIODIC_EN	 (1 << 14) // SMI on PERIODIC_STS in SMI_STS
+#define TCO_EN	 (1 << 13) // Enable TCO Logic (BIOSWE et al)
+#define MCSMI_EN	 (1 << 11) // Trap microcontroller range access
+#define BIOS_RLS	 (1 <<  7) // asserts SCI on bit set
+#define SWSMI_TMR_EN	 (1 <<  6) // start software smi timer on bit set
+#define APMC_EN	 (1 <<  5) // Writes to APM_CNT cause SMI#
+#define SLP_SMI_EN	 (1 <<  4) // Write to SLP_EN in PM1_CNT asserts SMI#
+#define LEGACY_USB_EN  (1 <<  3) // Legacy USB circuit SMI logic
+#define BIOS_EN	 (1 <<  2) // Assert SMI# on setting GBL_RLS bit
+#define EOS		 (1 <<  1) // End of SMI (deassert SMI#)
+#define GBL_SMI_EN	 (1 <<  0) // SMI# generation at all?
 #define SMI_STS		0x34
 #define ALT_GP_SMI_EN	0x38
 #define ALT_GP_SMI_STS	0x3a