[coreboot-gerrit] New patch to review for coreboot: 0efacc4 northbridge/intel/i945/i945.h: Trivial, fixup header guards

[Edward O'Callaghan (eocallaghan@alterapraxis.com)]

Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5896

-gerrit

commit 0efacc42d4732fd540fccdaeca3ef4f74667d2e9
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Sun Jun 1 16:09:21 2014 +1000

    northbridge/intel/i945/i945.h: Trivial, fixup header guards
    
    Change-Id: Iff15ab436e5b7b4e189c7341e7c508faaef07a3a
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/northbridge/intel/i945/i945.h | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index d4d35a2..728fe0a 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -17,8 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef __NORTHBRIDGE_INTEL_I945_I945_H__
-#define __NORTHBRIDGE_INTEL_I945_I945_H__ 1
+#ifndef NORTHBRIDGE_INTEL_I945_H
+#define NORTHBRIDGE_INTEL_I945_H
 
 /* Northbridge BARs */
 #define DEFAULT_PCIEXBAR	CONFIG_MMCONF_BASE_ADDRESS	/* 4 KB per PCIe device */
@@ -58,9 +58,10 @@
 #define  DEVEN_D1F0 (1 << 1)
 #define  DEVEN_D2F0 (1 << 3)
 #define  DEVEN_D2F1 (1 << 4)
+
 #ifndef BOARD_DEVEN
 #define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 )
-#endif
+#endif /* BOARD_DEVEN */
 
 #define BSM		0x5c
 
@@ -360,5 +361,6 @@ void dump_pci_devices(void);
 void dump_spd_registers(void);
 void dump_mem(unsigned start, unsigned end);
 
-#endif
-#endif
+#endif /* __ACPI__ */
+
+#endif /* NORTHBRIDGE_INTEL_I945_H */