[coreboot-gerrit] New patch to review for coreboot: 317d109 Southbridge i82801gx.h: add LPC Interface Generic Decode Range# 1, 2, 3 and 4
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Mon Jun 9 09:16:38 CEST 2014
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5961
-gerrit
commit 317d109825a8df4669d90df871775fa6f8ba59e7
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Mon Jun 9 09:13:41 2014 +0200
Southbridge i82801gx.h: add LPC Interface Generic Decode Range# 1,2,3 and 4
Change-Id: Idb68108042df501bb11e3856828ac24722a32835
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/southbridge/intel/i82801gx/i82801gx.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 1064dde..c998a9f 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -95,7 +95,11 @@ int smbus_read_byte(unsigned device, unsigned address);
#define PIRQH_ROUT 0x6B
#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
-#define LPC_EN 0x82 /* LPC IF Enables Register */
+#define LPC_EN 0x82 /* LPC Interface Enables Register */
+#define LPC_GEN1_DEC 0x84 /* LPC Interface Generic Decode Range 1 */
+#define LPC_GEN2_DEC 0x88 /* LPC Interface Generic Decode Range 2 */
+#define LPC_GEN3_DEC 0x8c /* LPC Interface Generic Decode Range 3 */
+#define LPC_GEN4_DEC 0x90 /* LPC Interface Generic Decode Range 4 */
/* PCI Configuration Space (D31:F1): IDE */
#define INTR_LN 0x3c
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