[coreboot-gerrit] Patch set updated for coreboot: cb97298 fsp_baytrail: Fix CONFIG_ENABLE_FSP_FAST_BOOT

[Martin Roth (gaumless@gmail.com)]

Martin Roth (gaumless at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5972

-gerrit

commit cb972982b3d621d3111af6994536bf04503b14be
Author: Martin Roth <martin.roth at se-eng.com>
Date:   Wed Jun 11 09:35:37 2014 -0600

    fsp_baytrail: Fix CONFIG_ENABLE_FSP_FAST_BOOT
    
    While pushing the fsp_baytrail code, it was requested that we change
    CONFIG_ENABLE_FAST_BOOT to CONFIG_ENABLE_FSP_FAST_BOOT.
    
    These were missed in the change.
    
    Change-Id: If8af3f90b0f5cc9154ff1d3a387f442430f42dee
    Signed-off-by: Martin Roth <martin.roth at se-eng.com>
---
 src/mainboard/intel/bayleybay_fsp/Kconfig         | 2 +-
 src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig
index eaf4f22..8dcc199 100644
--- a/src/mainboard/intel/bayleybay_fsp/Kconfig
+++ b/src/mainboard/intel/bayleybay_fsp/Kconfig
@@ -68,7 +68,7 @@ config FSP_FILE
 config MRC_CACHE_LOC_OVERRIDE
 	hex
 	default 0xfff80000
-	depends on ENABLE_FAST_BOOT
+	depends on ENABLE_FSP_FAST_BOOT
 
 config CBFS_SIZE
 	hex
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index 87fe5ae..60a1f7a 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -314,7 +314,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
 	pFspInitParams->NvsBufferPtr = NULL;
 	pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION;
 
-#if IS_ENABLED(CONFIG_ENABLE_FAST_BOOT)
+#if IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT)
 	/* Find the fastboot cache that was saved in the ROM */
 	pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache();
 #endif