[coreboot-gerrit] Patch set updated for coreboot: a9f415b lynxpoint: Use separate SMI callback for USB XHCI routing

[Matt DeVillier (matt.devillier@gmail.com)]

Matt DeVillier (matt.devillier at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6011

-gerrit

commit a9f415b2aa0deba7d22d97dbefec759318400108
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Aug 21 13:16:21 2013 -0700

    lynxpoint: Use separate SMI callback for USB XHCI routing
    
    This will allow the legacy mode boot path to leave USB
    ports routed to EHCI so they can be used by SeaBIOS.
    
    BUG=chrome-os-partner:22085
    BRANCH=falco,peppy
    TEST=manual: Build and boot from USB and SeaBIOS on falco
    
    Change-Id: I46870eccd1b846dc8a7f8d7948969c8e623e18cd
    Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66547
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/southbridge/intel/lynxpoint/smihandler.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index d1e9bbc..00e4a83 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -316,10 +316,8 @@ static void southbridge_smi_apmc(void)
 			printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
 		}
 		break;
-	case APM_CNT_FINALIZE:
-#if CONFIG_FINALIZE_USB_ROUTE_XHCI
+	case 0xca:
 		usb_xhci_route_all();
-#endif
 		break;
 #if CONFIG_ELOG_GSMI
 	case ELOG_GSMI_APM_CNT: