[coreboot-gerrit] New patch to review for coreboot: 31c4e99 intel boards: Use acpi_is_wakeup_s3()
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Fri Jun 20 09:38:51 CEST 2014
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6071
-gerrit
commit 31c4e99cf888bf2106f9a3cf0166a94e668ec873
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Thu Jun 19 19:50:51 2014 +0300
intel boards: Use acpi_is_wakeup_s3()
Change-Id: Icab0aeb2d5bf19b4029ca29b8a1e7564ef59a538
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/mainboard/google/bolt/ec.c | 2 +-
src/mainboard/google/falco/ec.c | 2 +-
src/mainboard/google/link/ec.c | 2 +-
src/mainboard/google/peppy/ec.c | 2 +-
src/mainboard/google/rambi/ec.c | 2 +-
src/mainboard/google/slippy/ec.c | 2 +-
src/mainboard/intel/emeraldlake2/ec.c | 2 +-
src/mainboard/samsung/lumpy/ec.c | 2 +-
src/soc/intel/baytrail/ehci.c | 2 +-
src/soc/intel/baytrail/elog.c | 2 +-
src/soc/intel/baytrail/refcode.c | 11 +----------
src/southbridge/intel/bd82x6x/elog.c | 2 +-
src/southbridge/intel/bd82x6x/lpc.c | 2 +-
src/southbridge/intel/bd82x6x/me.c | 5 +----
src/southbridge/intel/bd82x6x/me_8.x.c | 5 +----
src/southbridge/intel/fsp_bd82x6x/elog.c | 2 +-
src/southbridge/intel/fsp_bd82x6x/lpc.c | 2 +-
src/southbridge/intel/fsp_bd82x6x/me.c | 5 +----
src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 5 +----
src/southbridge/intel/i82801gx/lpc.c | 2 +-
src/southbridge/intel/i82801ix/lpc.c | 2 +-
src/southbridge/intel/ibexpeak/lpc.c | 2 +-
src/southbridge/intel/ibexpeak/me.c | 5 +----
src/southbridge/intel/lynxpoint/elog.c | 2 +-
src/southbridge/intel/lynxpoint/lpc.c | 4 ++--
src/southbridge/intel/lynxpoint/me_9.x.c | 4 +---
src/southbridge/intel/lynxpoint/usb_xhci.c | 4 +---
27 files changed, 28 insertions(+), 56 deletions(-)
diff --git a/src/mainboard/google/bolt/ec.c b/src/mainboard/google/bolt/ec.c
index 04a9931..e5ed4e8 100644
--- a/src/mainboard/google/bolt/ec.c
+++ b/src/mainboard/google/bolt/ec.c
@@ -29,7 +29,7 @@ void mainboard_ec_init(void)
post_code(0xf0);
/* Restore SCI event mask on resume. */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3()) {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S3_WAKE_EVENTS);
diff --git a/src/mainboard/google/falco/ec.c b/src/mainboard/google/falco/ec.c
index 04a9931..e5ed4e8 100644
--- a/src/mainboard/google/falco/ec.c
+++ b/src/mainboard/google/falco/ec.c
@@ -29,7 +29,7 @@ void mainboard_ec_init(void)
post_code(0xf0);
/* Restore SCI event mask on resume. */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3()) {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S3_WAKE_EVENTS);
diff --git a/src/mainboard/google/link/ec.c b/src/mainboard/google/link/ec.c
index 7dfadeb..1f56555 100644
--- a/src/mainboard/google/link/ec.c
+++ b/src/mainboard/google/link/ec.c
@@ -29,7 +29,7 @@ void link_ec_init(void)
post_code(0xf0);
/* Restore SCI event mask on resume. */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3()) {
google_chromeec_log_events(LINK_EC_LOG_EVENTS |
LINK_EC_S3_WAKE_EVENTS);
diff --git a/src/mainboard/google/peppy/ec.c b/src/mainboard/google/peppy/ec.c
index 04a9931..e5ed4e8 100644
--- a/src/mainboard/google/peppy/ec.c
+++ b/src/mainboard/google/peppy/ec.c
@@ -29,7 +29,7 @@ void mainboard_ec_init(void)
post_code(0xf0);
/* Restore SCI event mask on resume. */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3()) {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S3_WAKE_EVENTS);
diff --git a/src/mainboard/google/rambi/ec.c b/src/mainboard/google/rambi/ec.c
index a6d2161..238f795 100644
--- a/src/mainboard/google/rambi/ec.c
+++ b/src/mainboard/google/rambi/ec.c
@@ -29,7 +29,7 @@ void mainboard_ec_init(void)
post_code(0xf0);
/* Restore SCI event mask on resume. */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3()) {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S3_WAKE_EVENTS);
diff --git a/src/mainboard/google/slippy/ec.c b/src/mainboard/google/slippy/ec.c
index 04a9931..e5ed4e8 100644
--- a/src/mainboard/google/slippy/ec.c
+++ b/src/mainboard/google/slippy/ec.c
@@ -29,7 +29,7 @@ void mainboard_ec_init(void)
post_code(0xf0);
/* Restore SCI event mask on resume. */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3()) {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S3_WAKE_EVENTS);
diff --git a/src/mainboard/intel/emeraldlake2/ec.c b/src/mainboard/intel/emeraldlake2/ec.c
index b50ab65..9f2a944 100644
--- a/src/mainboard/intel/emeraldlake2/ec.c
+++ b/src/mainboard/intel/emeraldlake2/ec.c
@@ -27,7 +27,7 @@ void lumpy_ec_init(void)
{
printk(BIOS_DEBUG, "lumpy_ec_init\n");
- if (acpi_slp_type == 3)
+ if (acpi_is_wakeup_s3())
return;
/*
diff --git a/src/mainboard/samsung/lumpy/ec.c b/src/mainboard/samsung/lumpy/ec.c
index 2406012..c86ec27 100644
--- a/src/mainboard/samsung/lumpy/ec.c
+++ b/src/mainboard/samsung/lumpy/ec.c
@@ -27,7 +27,7 @@ void lumpy_ec_init(void)
{
printk(BIOS_DEBUG, "lumpy_ec_init\n");
- if (acpi_slp_type == 3)
+ if (acpi_is_wakeup_s3())
return;
/*
diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c
index d4e2986..5d1a4d8 100644
--- a/src/soc/intel/baytrail/ehci.c
+++ b/src/soc/intel/baytrail/ehci.c
@@ -143,7 +143,7 @@ static void ehci_init(device_t dev)
};
/* Don't reset controller in S3 resume path */
- if (acpi_slp_type != 3)
+ if (!acpi_is_wakeup_s3())
reg_script_run_on_dev(dev, ehci_hc_reset);
/* Disable controller if ports are routed to XHCI */
diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c
index 8c6be9f..c31bb00 100644
--- a/src/soc/intel/baytrail/elog.c
+++ b/src/soc/intel/baytrail/elog.c
@@ -73,7 +73,7 @@ static void log_wake_events(const struct chipset_power_state *ps)
if (ps->pm1_sts & WAK_STS) {
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
- acpi_slp_type == 3 ? 3 : 5);
+ acpi_is_wakeup_s3() ? 3 : 5);
}
if (ps->pm1_sts & PWRBTN_STS) {
diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c
index 019e0a5..12e3ed4 100644
--- a/src/soc/intel/baytrail/refcode.c
+++ b/src/soc/intel/baytrail/refcode.c
@@ -29,15 +29,6 @@
#include <baytrail/ramstage.h>
#include <baytrail/efi_wrapper.h>
-static inline int is_s3_resume(void)
-{
-#if CONFIG_HAVE_ACPI_RESUME
- return acpi_slp_type == 3;
-#else
- return 0;
-#endif
-}
-
static inline struct ramstage_cache *next_cache(struct ramstage_cache *c)
{
return (struct ramstage_cache *)&c->program[c->size];
@@ -140,7 +131,7 @@ static efi_wrapper_entry_t load_reference_code(void)
};
int ret;
- if (is_s3_resume()) {
+ if (acpi_is_wakeup_s3()) {
return load_refcode_from_cache();
}
diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c
index 09dfcdb..55fe06f 100644
--- a/src/southbridge/intel/bd82x6x/elog.c
+++ b/src/southbridge/intel/bd82x6x/elog.c
@@ -80,7 +80,7 @@ void pch_log_state(void)
/* ACPI Wake */
if (pm1_sts & (1 << 15))
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
- acpi_slp_type == 3 ? 3 : 5);
+ acpi_is_wakeup_s3() ? 3 : 5);
/*
* Wake sources
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index e052150..7629895 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -431,7 +431,7 @@ static void pch_lock_smm(struct device *dev)
u8 reg8;
#endif
- if (acpi_slp_type != 3) {
+ if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(0xe1, 0xb2); // Enable ACPI mode
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 17be63b..44c7273 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -554,12 +554,9 @@ static me_bios_path intel_me_path(device_t dev)
struct me_hfs hfs;
struct me_gmes gmes;
-#if CONFIG_HAVE_ACPI_RESUME
/* S3 wake skips all MKHI messages */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3())
return ME_S3WAKE_BIOS_PATH;
- }
-#endif
pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES);
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index b12a1e6..356d9a5 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -535,12 +535,9 @@ static me_bios_path intel_me_path(device_t dev)
struct me_hfs hfs;
struct me_gmes gmes;
-#if CONFIG_HAVE_ACPI_RESUME
/* S3 wake skips all MKHI messages */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3())
return ME_S3WAKE_BIOS_PATH;
- }
-#endif
pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES);
diff --git a/src/southbridge/intel/fsp_bd82x6x/elog.c b/src/southbridge/intel/fsp_bd82x6x/elog.c
index 09dfcdb..55fe06f 100644
--- a/src/southbridge/intel/fsp_bd82x6x/elog.c
+++ b/src/southbridge/intel/fsp_bd82x6x/elog.c
@@ -80,7 +80,7 @@ void pch_log_state(void)
/* ACPI Wake */
if (pm1_sts & (1 << 15))
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
- acpi_slp_type == 3 ? 3 : 5);
+ acpi_is_wakeup_s3() ? 3 : 5);
/*
* Wake sources
diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c
index 2633a49..4351e00 100644
--- a/src/southbridge/intel/fsp_bd82x6x/lpc.c
+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c
@@ -406,7 +406,7 @@ static void pch_lock_smm(struct device *dev)
u8 reg8;
#endif
- if (acpi_slp_type != 3) {
+ if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(0xe1, 0xb2); // Enable ACPI mode
diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c
index c61d12b..2282378 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me.c
@@ -553,12 +553,9 @@ static me_bios_path intel_me_path(device_t dev)
struct me_hfs hfs;
struct me_gmes gmes;
-#if CONFIG_HAVE_ACPI_RESUME
/* S3 wake skips all MKHI messages */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3())
return ME_S3WAKE_BIOS_PATH;
- }
-#endif
pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES);
diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
index 8e9a93a..1c2ab34 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
@@ -533,12 +533,9 @@ static me_bios_path intel_me_path(device_t dev)
struct me_hfs hfs;
struct me_gmes gmes;
-#if CONFIG_HAVE_ACPI_RESUME
/* S3 wake skips all MKHI messages */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3())
return ME_S3WAKE_BIOS_PATH;
- }
-#endif
pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES);
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index b9caac6..b208339 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -330,7 +330,7 @@ static void i82801gx_lock_smm(struct device *dev)
u8 reg8;
#endif
- if (acpi_slp_type != 3) {
+ if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 61a11b3..e8b9f65 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -374,7 +374,7 @@ static void i82801ix_lock_smm(struct device *dev)
u8 reg8;
#endif
- if (acpi_slp_type != 3) {
+ if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index dca4601..ef9a632 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -438,7 +438,7 @@ static void pch_lock_smm(struct device *dev)
u8 reg8;
#endif
- if (acpi_slp_type != 3) {
+ if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(0xe1, 0xb2); // Enable ACPI mode
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index 0e1b5b8..3130631 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -436,12 +436,9 @@ static me_bios_path intel_me_path(device_t dev)
struct me_hfs hfs;
struct me_gmes gmes;
-#if CONFIG_HAVE_ACPI_RESUME
/* S3 wake skips all MKHI messages */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3())
return ME_S3WAKE_BIOS_PATH;
- }
-#endif
pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES);
diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c
index 9ba3a98..a2352b3 100644
--- a/src/southbridge/intel/lynxpoint/elog.c
+++ b/src/southbridge/intel/lynxpoint/elog.c
@@ -161,7 +161,7 @@ void pch_log_state(void)
/* ACPI Wake */
if (pm1_sts & (1 << 15))
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
- acpi_slp_type == 3 ? 3 : 5);
+ acpi_is_wakeup_s3() ? 3 : 5);
/*
* Wake sources
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 5d1bcdd..6f40637 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -499,7 +499,7 @@ static void enable_lp_clock_gating(device_t dev)
static void pch_set_acpi_mode(void)
{
#if CONFIG_HAVE_SMI_HANDLER
- if (acpi_slp_type != 3) {
+ if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT);
@@ -716,7 +716,7 @@ static void pch_lpc_read_resources(device_t dev)
/* Allocate ACPI NVS in CBMEM */
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
- if (acpi_slp_type != 3 && gnvs)
+ if (!acpi_is_wakeup_s3() && gnvs)
memset(gnvs, 0, sizeof(global_nvs_t));
}
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index d3dfcfb..7ccdd22 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -878,13 +878,11 @@ static struct pci_operations pci_ops = {
static void intel_me_enable(device_t dev)
{
-#if CONFIG_HAVE_ACPI_RESUME
/* Avoid talking to the device in S3 path */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3()) {
dev->enabled = 0;
pch_disable_devfn(dev);
}
-#endif
}
static struct device_operations device_ops = {
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index 500b578..9978c49 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -394,11 +394,9 @@ static void usb_xhci_init(device_t dev)
reg32 |= (1 << 31);
pci_write_config32(dev, 0x40, reg32);
-#if CONFIG_HAVE_ACPI_RESUME
/* Enable ports that are disabled before returning to OS */
- if (acpi_slp_type == 3)
+ if (acpi_is_wakeup_s3())
usb_xhci_enable_ports_usb3(dev);
-#endif
}
static void usb_xhci_set_subsystem(device_t dev, unsigned vendor,
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