[coreboot-gerrit] New patch to review for coreboot: 426cde8 AGESA boards: Add prepare_for_resume()
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Fri Jun 20 17:20:55 CEST 2014
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6084
-gerrit
commit 426cde8efc1f34c9ae5735aea308dc7a07b6cea7
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Wed Jun 18 09:55:26 2014 +0300
AGESA boards: Add prepare_for_resume()
Use one common implementation for all AGESA platforms.
Change-Id: I410f8e0a9c75445882d67659cde00004eb7ad6b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/amd/agesa/s3_resume.c | 42 ++++++++++++++++++-------
src/cpu/amd/agesa/s3_resume.h | 5 +--
src/mainboard/amd/olivehill/romstage.c | 25 +--------------
src/mainboard/amd/parmer/romstage.c | 25 +--------------
src/mainboard/amd/persimmon/romstage.c | 26 +--------------
src/mainboard/amd/thatcher/romstage.c | 25 +--------------
src/mainboard/asrock/imb-a180/romstage.c | 25 +--------------
src/mainboard/asus/f2a85-m/romstage.c | 25 +--------------
src/mainboard/gizmosphere/gizmo/romstage.c | 26 +--------------
src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 25 +--------------
src/mainboard/jetway/nf81-t56n-lf/romstage.c | 26 +--------------
src/mainboard/lippert/frontrunner-af/romstage.c | 26 +--------------
src/mainboard/lippert/toucan-af/romstage.c | 26 +--------------
13 files changed, 42 insertions(+), 285 deletions(-)
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 2efe6be..4244786 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -22,6 +22,7 @@
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/amd/car.h>
#include <cpu/amd/mtrr.h>
#include <cpu/x86/cache.h>
#include <cbmem.h>
@@ -142,7 +143,8 @@ void restore_mtrr(void)
wrmsr(SYS_CFG, msr_data);
}
-void *backup_resume(void)
+#ifdef __PRE_RAM__
+static void *backup_resume(void)
{
void *resume_backup_memory;
@@ -160,7 +162,7 @@ void *backup_resume(void)
return resume_backup_memory;
}
-void move_stack_high_mem(void)
+static void move_stack_high_mem(void)
{
void *high_stack;
@@ -173,6 +175,7 @@ void move_stack_high_mem(void)
(high_stack - BSP_STACK_BASE_ADDR)
:);
}
+#endif
#ifndef __PRE_RAM__
static void write_mtrr(struct spi_flash *flash, u32 *p_nvram_pos, unsigned idx)
@@ -306,7 +309,8 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
}
#endif
-void set_resume_cache(void)
+#ifdef __PRE_RAM__
+static void set_resume_cache(void)
{
msr_t msr;
@@ -331,14 +335,28 @@ void set_resume_cache(void)
enable_cache();
}
-void s3_resume(void)
+void prepare_for_resume(void)
{
- int status;
-
- printk(BIOS_DEBUG, "agesawrapper_amds3laterestore ");
- status = agesawrapper_amds3laterestore();
- if (status)
- printk(BIOS_DEBUG, "error level: %x \n", (u32) status);
- else
- printk(BIOS_DEBUG, "passed.\n");
+ printk(BIOS_DEBUG, "Find resume memory location\n");
+ void *resume_backup_memory = backup_resume();
+
+ post_code(0x62);
+ printk(BIOS_DEBUG, "Move CAR stack.\n");
+ move_stack_high_mem();
+ printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
+
+ post_code(0x63);
+ disable_cache_as_ram();
+ printk(BIOS_DEBUG, "CAR disabled.\n");
+ set_resume_cache();
+
+ /*
+ * Copy the system memory that is in the ramstage area to the
+ * reserved area.
+ */
+ if (resume_backup_memory)
+ memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
+
+ printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
}
+#endif
diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h
index fd3f29e..b72e8a2 100644
--- a/src/cpu/amd/agesa/s3_resume.h
+++ b/src/cpu/amd/agesa/s3_resume.h
@@ -27,10 +27,7 @@ typedef enum {
} S3_DATA_TYPE;
void restore_mtrr(void);
-void s3_resume(void);
-void *backup_resume(void);
-void set_resume_cache(void);
-void move_stack_high_mem(void);
+void prepare_for_resume(void);
u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data);
void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data);
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 73cd40a..803c754 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -40,9 +40,6 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
@@ -132,27 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = (void *)backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 668dfc8..5f14997 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -40,9 +40,6 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
val = agesawrapper_amdinitmmio();
hudson_lpc_port80();
@@ -115,27 +112,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = (void *)backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 9ba34e7..e90c1b5 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -49,10 +49,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
-
/*
* All cores: allow caching of flash chip code and data
* (there are no cache-as-ram reliability concerns with family 14h)
@@ -144,27 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 1a7a399..0b719ac 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -45,9 +45,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val;
u8 byte;
device_t dev;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
val = agesawrapper_amdinitmmio();
hudson_lpc_port80();
@@ -132,27 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = (void *)backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 8ce496b..3d52619 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -45,9 +45,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val, t32;
u32 *addr32;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
@@ -156,27 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = (void *)backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index 3884e36..8d16b2f 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -74,9 +74,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
hudson_lpc_port80();
#endif
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
val = agesawrapper_amdinitmmio();
if (!cpu_init_detectedx && boot_cpu()) {
@@ -180,27 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = (void *)backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 11ae623..76e7dcb 100755
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -50,10 +50,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val;
msr_t msr;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
-
/*
* All cores: allow caching of flash chip code and data
* (there are no cache-as-ram reliability concerns with family 14h)
@@ -152,27 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
index 2be2bc5..db7883c 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
@@ -37,9 +37,6 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
val = agesawrapper_amdinitmmio();
hudson_lpc_port80();
@@ -112,27 +109,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = (void *)backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index bfd24cb..0c3597e 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -65,10 +65,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
-
/*
* All cores: allow caching of flash chip code and data
* (there are no cache-as-ram reliability concerns with family 14h)
@@ -160,27 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif /* CONFIG_HAVE_ACPI_RESUME */
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index 7146c01..a569e64 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -48,10 +48,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
-
/*
* All cores: allow caching of flash chip code and data
* (there are no cache-as-ram reliability concerns with family 14h)
@@ -147,27 +143,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index accf381..c9ad6de 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -49,10 +49,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
-
/*
* All cores: allow caching of flash chip code and data
* (there are no cache-as-ram reliability concerns with family 14h)
@@ -148,27 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
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