[coreboot-gerrit] New patch to review for coreboot: b6e55f3 southbridge/amd/rsXY0/cmn.c: Incorrect usage of logical vs. bitwise and

[Edward O'Callaghan (eocallaghan@alterapraxis.com)]

Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6147

-gerrit

commit b6e55f35d144595e311a0d2690b0a85838796576
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Sat Jun 28 15:36:57 2014 +1000

    southbridge/amd/rsXY0/cmn.c: Incorrect usage of logical vs. bitwise and
    
    Spotted by Clang.
    
    Change-Id: I26e7acddbff32e978c2bf984c21d9a63337067f8
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/southbridge/amd/rs690/cmn.c | 2 +-
 src/southbridge/amd/rs780/cmn.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c
index 36870b3..b00c72b 100644
--- a/src/southbridge/amd/rs690/cmn.c
+++ b/src/southbridge/amd/rs690/cmn.c
@@ -289,7 +289,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 				reg =
 				    nbpcie_p_read_index(dev,
 							PCIE_LC_LINK_WIDTH);
-				tmp = (reg >> 4) && 0x3;	/* get bit4-6 */
+				tmp = (reg >> 4) & 0x3;	/* get bit4-6 */
 				reg &= 0xfff8;	/* clear bit0-2 */
 				reg += tmp;	/* merge */
 				reg |= 1 << 8;
diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c
index cf09b9a..a5b3c81 100644
--- a/src/southbridge/amd/rs780/cmn.c
+++ b/src/southbridge/amd/rs780/cmn.c
@@ -330,7 +330,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 				reg =
 				    nbpcie_p_read_index(dev,
 							PCIE_LC_LINK_WIDTH);
-				tmp = (reg >> 4) && 0x3;	/* get bit4-6 */
+				tmp = (reg >> 4) & 0x3;	/* get bit4-6 */
 				reg &= 0xfff8;	/* clear bit0-2 */
 				reg += tmp;	/* merge */
 				reg |= 1 << 8;