[coreboot-gerrit] New patch to review for coreboot: b3f48d2 vendorcode/amd/agesa: Spell *sync* without *h* in comments
Paul Menzel (paulepanter@users.sourceforge.net)
gerrit at coreboot.org
Sat Jun 28 10:31:06 CEST 2014
Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6152
-gerrit
commit b3f48d226e15432797035a78cbe8cd085de13d82
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date: Sat Jun 28 09:06:57 2014 +0200
vendorcode/amd/agesa: Spell *sync* without *h* in comments
Run the following command to fix all occurrences in vendor code.
$ git grep -l "synch " | xargs sed -i 's/synch /sync /g'
Change-Id: I8395cd289c8d713cf89f186cc9bbc4c478dcb743
Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h | 2 +-
src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h | 2 +-
src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h | 2 +-
src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h | 2 +-
src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h | 2 +-
src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h | 2 +-
src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h | 2 +-
src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h | 2 +-
src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c | 2 +-
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h | 2 +-
src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h | 2 +-
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h | 2 +-
src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h | 2 +-
src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c | 2 +-
14 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h
index 475272d..bc4c5c3 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h
@@ -182,7 +182,7 @@ typedef enum {
} TABLE_CORE_SELECTOR;
// Initializer bit pattern values for platform features.
-// Keep in synch with the PLATFORM_FEATURES struct!
+// Keep in sync with the PLATFORM_FEATURES struct!
// The 5 control flow modes.
#define AMD_PF_NFCM BIT0
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h
index 5059dce..79dd2b1 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h
@@ -55,7 +55,7 @@
/// For event ::HT_EVENT_HW_SYNCFLOOD
typedef struct {
UINT32 Node; ///< The Node on which observed
- UINT32 Link; ///< The Link on that Node which reported synch flood
+ UINT32 Link; ///< The Link on that Node which reported sync flood
UINT32 Reserved1; ///< Reserved.
UINT32 Reserved2; ///< Reserved.
} HT_EVENT_DATA_HW_SYNCFLOOD;
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h
index cb27aee..cde716f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h
@@ -186,7 +186,7 @@ typedef enum {
} TABLE_CORE_SELECTOR;
// Initializer bit pattern values for platform features.
-// Keep in synch with the PLATFORM_FEATURES struct!
+// Keep in sync with the PLATFORM_FEATURES struct!
// The 5 control flow modes.
#define AMD_PF_NFCM BIT0
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h
index b3b4a90..bc62f8a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h
@@ -55,7 +55,7 @@
/// For event ::HT_EVENT_HW_SYNCFLOOD
typedef struct {
UINT32 Node; ///< The Node on which observed
- UINT32 Link; ///< The Link on that Node which reported synch flood
+ UINT32 Link; ///< The Link on that Node which reported sync flood
UINT32 Reserved1; ///< Reserved.
UINT32 Reserved2; ///< Reserved.
} HT_EVENT_DATA_HW_SYNCFLOOD;
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h
index 76ec4b0..24d2209 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h
@@ -187,7 +187,7 @@ typedef enum {
} TABLE_CORE_SELECTOR;
// Initializer bit pattern values for platform features.
-// Keep in synch with the PLATFORM_FEATURES struct!
+// Keep in sync with the PLATFORM_FEATURES struct!
// The 5 control flow modes.
#define AMD_PF_NFCM BIT0
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h
index f7f846a..fd2267b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h
@@ -56,7 +56,7 @@
/// For event ::HT_EVENT_HW_SYNCFLOOD
typedef struct {
UINT32 Node; ///< The Node on which observed
- UINT32 Link; ///< The Link on that Node which reported synch flood
+ UINT32 Link; ///< The Link on that Node which reported sync flood
UINT32 Reserved1; ///< Reserved.
UINT32 Reserved2; ///< Reserved.
} HT_EVENT_DATA_HW_SYNCFLOOD;
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h
index 16c3baa..e3388ce 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h
@@ -187,7 +187,7 @@ typedef enum {
} TABLE_CORE_SELECTOR;
// Initializer bit pattern values for platform features.
-// Keep in synch with the PLATFORM_FEATURES struct!
+// Keep in sync with the PLATFORM_FEATURES struct!
// The 5 control flow modes.
#define AMD_PF_NFCM BIT0
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h
index 9e28445..457cc02 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h
@@ -56,7 +56,7 @@
/// For event ::HT_EVENT_HW_SYNCFLOOD
typedef struct {
UINT32 Node; ///< The Node on which observed
- UINT32 Link; ///< The Link on that Node which reported synch flood
+ UINT32 Link; ///< The Link on that Node which reported sync flood
UINT32 Reserved1; ///< Reserved.
UINT32 Reserved2; ///< Reserved.
} HT_EVENT_DATA_HW_SYNCFLOOD;
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c
index d154e2f..9448a7a 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c
@@ -419,7 +419,7 @@ MemNAfterDQSTrainingOr (
MemNSwitchDCTNb (NBPtr, Dct);
if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
if (!(NBPtr->DctCachePtr->Is__x4)) {
- // Only synch when 1D training has been performed or training with x8 DIMMs
+ // Only sync when 1D training has been performed or training with x8 DIMMs
for (Dimm = 0; Dimm < 4; Dimm++) {
for (Byte = 0; Byte < 9; Byte++) {
Dly = (UINT16) MemNGetTrainDlyNb (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, Byte));
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h
index c21cb9c..48c5452 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h
@@ -186,7 +186,7 @@ typedef enum {
} TABLE_CORE_SELECTOR;
// Initializer bit pattern values for platform features.
-// Keep in synch with the PLATFORM_FEATURES struct!
+// Keep in sync with the PLATFORM_FEATURES struct!
// The 5 control flow modes.
#define AMD_PF_NFCM BIT0
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h
index 6507165..74ea10d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h
@@ -55,7 +55,7 @@
/// For event ::HT_EVENT_HW_SYNCFLOOD
typedef struct {
UINT32 Node; ///< The Node on which observed
- UINT32 Link; ///< The Link on that Node which reported synch flood
+ UINT32 Link; ///< The Link on that Node which reported sync flood
UINT32 Reserved1; ///< Reserved.
UINT32 Reserved2; ///< Reserved.
} HT_EVENT_DATA_HW_SYNCFLOOD;
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h
index 1f6341a..7696047 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h
@@ -204,7 +204,7 @@ typedef enum {
#define PERFORM_EARLY_ANY_CONDITION (PERFORM_EARLY_WARM_RESET | PERFORM_EARLY_COLD_BOOT)
// Initializer bit pattern values for platform features.
-// Keep in synch with the PLATFORM_FEATURES struct!
+// Keep in sync with the PLATFORM_FEATURES struct!
// The 5 control flow modes.
#define AMD_PF_NFCM BIT0
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h
index 58d0cbe..0c208cb 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h
@@ -55,7 +55,7 @@
/// For event ::HT_EVENT_HW_SYNCFLOOD
typedef struct {
UINT32 Node; ///< The Node on which observed
- UINT32 Link; ///< The Link on that Node which reported synch flood
+ UINT32 Link; ///< The Link on that Node which reported sync flood
UINT32 Reserved1; ///< Reserved.
UINT32 Reserved2; ///< Reserved.
} HT_EVENT_DATA_HW_SYNCFLOOD;
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c
index be956bc..23969b3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c
@@ -403,7 +403,7 @@ MemNAfterDQSTrainingKB (
MemNSwitchDCTNb (NBPtr, Dct);
if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
if (!(NBPtr->DctCachePtr->Is2Dx4)) {
- // Only synch when 1D training has been performed or 2D training with x8 DIMMs
+ // Only sync when 1D training has been performed or 2D training with x8 DIMMs
for (Dimm = 0; Dimm < 4; Dimm++) {
for (Byte = 0; Byte < 9; Byte++) {
Dly = (UINT16) MemNGetTrainDlyNb (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, Byte));
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