[coreboot-gerrit] Patch set updated for coreboot: b8db3c8 cpu/amd/geode_gx2/cache_as_ram.inc: Remove illegal ASCII art

[Edward O'Callaghan (eocallaghan@alterapraxis.com)]

Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6154

-gerrit

commit b8db3c831ef3c10ffc7fcdfc19c0d0330e4165f6
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Sat Jun 28 19:07:33 2014 +1000

    cpu/amd/geode_gx2/cache_as_ram.inc: Remove illegal ASCII art
    
    Embedding comments inside comments is illegal in the C specification,
    Clang enforces this.
    
    Change-Id: I0a468e4196034b00dfc5860fdbbab7788e4fef77
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/cpu/amd/geode_gx2/cache_as_ram.inc | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc
index 6a107fe..45a04f8 100644
--- a/src/cpu/amd/geode_gx2/cache_as_ram.inc
+++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc
@@ -26,17 +26,17 @@
 #define	GX2_CACHEWAY_SIZE	(GX2_NUM_CACHELINES * GX2_CACHELINE_SIZE)
 #define	CR0_CD				0x40000000	/* bit 30 = Cache Disable */
 #define	CR0_NW				0x20000000	/* bit 29 = Not Write Through */
+
 #include <cpu/amd/gx2def.h>
 #include <cpu/x86/post_code.h>
-/***************************************************************************
-/**
-/**	DCacheSetup
-/**
-/**	Setup data cache for  use as RAM for a stack.
-/**
-/**	Max. size data cache =0x4000 (16KB)
-/**
-/***************************************************************************/
+
+/*
+ *	DCacheSetup
+ *
+ *	Setup data cache for use as RAM for a stack.
+ *
+ *	Max. size data cache =0x4000 (16KB)
+ */
 DCacheSetup:
 	/* Save the BIST result */
 	movl    %eax, %ebx
@@ -201,4 +201,3 @@ __main:
 	post_code(POST_DEAD_CODE)
 	hlt
 	jmp	.Lhlt
-