[coreboot-gerrit] New patch to review for coreboot: 756f414 intel/jarrell: Apply ROMCC workaround

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5348

-gerrit

commit 756f414062cf42770d00f8ed8686dbd89a3e6f15
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Thu Mar 6 16:32:18 2014 +0200

    intel/jarrell: Apply ROMCC workaround
    
    Taken from intel/xe7501devkit, maybe it had same symptoms once.
    
    The call to ich5_watchdog_on() has side-effect of exploding the
    requirements for ROMCC internal arrays at compile-time. The hard-coded
    limit in question is MAX_RHS in util/romcc.c, the default of 127 comes
    from the rhs field defined with 7 bits.
    
    Before this patch intel/jarrell builds were using upto MAX_RHS=102, while
    other ROMCC boards built even with MAX_RHS=10. This workaround brings
    intel/jarrell to the same level.
    
    Change-Id: I162d801f81d9196403d88636eb9cb291c950ded0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/mainboard/intel/jarrell/romstage.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
index c6f014c..921820f 100644
--- a/src/mainboard/intel/jarrell/romstage.c
+++ b/src/mainboard/intel/jarrell/romstage.c
@@ -102,4 +102,7 @@ static void main(unsigned long bist)
 	dump_pci_device(PCI_DEV(0, 0x00, 0));
 	dump_bar14(PCI_DEV(0, 0x00, 0));
 #endif
+	// NOTE: ROMCC dies with an internal compiler error
+	//		 if the following line is removed.
+	print_debug("SDRAM is up.\n");
 }