[coreboot-gerrit] Patch merged into coreboot/master: 56fc285 intel/jarrell: Apply ROMCC workaround
gerrit at coreboot.org
gerrit at coreboot.org
Sun Mar 9 13:09:54 CET 2014
the following patch was just integrated into master:
commit 56fc2858723187bc94160240b4a8af1250bcc443
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Thu Mar 6 16:32:18 2014 +0200
intel/jarrell: Apply ROMCC workaround
Taken from intel/xe7501devkit, maybe it had same symptoms once.
The call to ich5_watchdog_on() has side-effect of exploding the
requirements for ROMCC internal arrays at compile-time. The hard-coded
limit in question is MAX_RHS in util/romcc.c, the default of 127 comes
from the rhs field defined with 7 bits.
Before this patch intel/jarrell builds were using upto MAX_RHS=102, while
other ROMCC boards built even with MAX_RHS=10. This workaround brings
intel/jarrell to the same level.
Change-Id: I162d801f81d9196403d88636eb9cb291c950ded0
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
See http://review.coreboot.org/5348 for details.
-gerrit
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