[coreboot-gerrit] Patch set updated for coreboot: 959f6d0 ChromeOS: Rename init_chromeos() to init_trusted_platform()
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Sat May 3 12:28:26 CEST 2014
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5644
-gerrit
commit 959f6d049f8a7acb318be0770bddf90c7a8740cd
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Fri Dec 20 23:57:17 2013 +0200
ChromeOS: Rename init_chromeos() to init_trusted_platform()
The function does TPM hardware initialisation but is not really
related to use of ChromeOS.
Change-Id: Ie67c6e2b07485bdf861f74f9a8768882d9495a01
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/intel/haswell/romstage.c | 8 ++------
src/drivers/pc80/Kconfig | 9 +++++++++
src/include/bootmode.h | 1 +
src/lib/bootmode.c | 26 ++++++++++++++++++++++++++
src/mainboard/google/butterfly/chromeos.c | 2 +-
src/mainboard/google/butterfly/romstage.c | 8 ++------
src/mainboard/google/link/chromeos.c | 2 +-
src/mainboard/google/link/romstage.c | 8 ++------
src/mainboard/google/parrot/chromeos.c | 2 +-
src/mainboard/google/parrot/romstage.c | 8 ++------
src/mainboard/google/pit/chromeos.c | 2 +-
src/mainboard/google/snow/chromeos.c | 2 +-
src/mainboard/google/stout/acpi_tables.c | 2 +-
src/mainboard/google/stout/chromeos.c | 2 +-
src/mainboard/google/stout/romstage.c | 7 +------
src/mainboard/intel/emeraldlake2/chromeos.c | 2 +-
src/mainboard/intel/emeraldlake2/romstage.c | 8 ++------
src/mainboard/samsung/lumpy/romstage.c | 7 +------
src/mainboard/samsung/stumpy/romstage.c | 7 +------
src/vendorcode/google/chromeos/Kconfig | 8 --------
src/vendorcode/google/chromeos/chromeos.h | 2 +-
src/vendorcode/google/chromeos/vboot.c | 24 +-----------------------
22 files changed, 59 insertions(+), 88 deletions(-)
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 9e27668..a77cb0c 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -36,9 +36,7 @@
#include <ramstage_cache.h>
#include <romstage_handoff.h>
#include <reset.h>
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
+#include <bootmode.h>
#if CONFIG_EC_GOOGLE_CHROMEEC
#include <ec/google/chromeec/ec.h>
#endif
@@ -279,9 +277,7 @@ void romstage_common(const struct romstage_params *params)
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
post_code(0x3f);
-#if CONFIG_CHROMEOS
- init_chromeos(boot_mode);
-#endif
+ init_trusted_platform(boot_mode);
timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/drivers/pc80/Kconfig b/src/drivers/pc80/Kconfig
index 485dd64..656d361 100644
--- a/src/drivers/pc80/Kconfig
+++ b/src/drivers/pc80/Kconfig
@@ -23,3 +23,12 @@ config TPM
Enable this option to enable TPM support in coreboot.
If unsure, say N.
+
+config NO_TPM_RESUME
+ bool
+ default n
+ depends on TPM
+ help
+ On some boards the TPM stays powered up in S3. On those
+ boards, booting Windows will break if the TPM resume command
+ is sent during an S3 resume.
diff --git a/src/include/bootmode.h b/src/include/bootmode.h
index 323668b..63b5abc 100644
--- a/src/include/bootmode.h
+++ b/src/include/bootmode.h
@@ -37,4 +37,5 @@ static inline int recovery_mode_enabled(void) { return 0; }
static inline int developer_mode_enabled(void) { return 0; }
#endif
+void init_trusted_platform(int bootmode);
#endif /* __BOOTMODE_H__ */
diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c
index 9818490..2f815d3 100644
--- a/src/lib/bootmode.c
+++ b/src/lib/bootmode.c
@@ -18,6 +18,8 @@
*/
#include <rules.h>
+#include <kconfig.h>
+#include <console/console.h>
#include <bootmode.h>
#if CONFIG_CHROMEOS || CONFIG_VBOOT_VERIFY_FIRMWARE
#include <vendorcode/google/chromeos/chromeos.h>
@@ -78,3 +80,27 @@ void gfx_set_init_done(int done)
gfx_init_done = done;
}
#endif
+
+#if ENV_ROMSTAGE
+void init_trusted_platform(int bootmode)
+{
+#if IS_ENABLED(CONFIG_TPM)
+ /* With CONFIG_CHROMEOS, u-boot does TPM init on power-on.
+ * Doing TPM startup when we're not coming in on the S3 resume path
+ * saves us roughly 20ms in boot time only. This does not seem to
+ * be worth an API change to vboot_reference-firmware right now, so
+ * just bail out early:
+ */
+ if (IS_ENABLED(CONFIG_CHROMEOS) && bootmode != 2)
+ return;
+
+ /* On some boards the TPM stays powered up in S3. */
+ if (IS_ENABLED(CONFIG_NO_TPM_RESUME) && bootmode == 2)
+ return;
+
+ init_vboot(bootmode);
+#else
+ printk(BIOS_DEBUG, "TPM: support not enabled in build.\n");
+#endif
+}
+#endif
diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c
index 8f249c6..61097c3 100644
--- a/src/mainboard/google/butterfly/chromeos.c
+++ b/src/mainboard/google/butterfly/chromeos.c
@@ -19,7 +19,7 @@
#include <console/console.h>
#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
+#include <bootmode.h>
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index d32f3f0..0b2f5c9 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -38,9 +38,7 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include "gpio.h"
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
+#include <bootmode.h>
#include <cbfs.h>
static void pch_enable_lpc(void)
@@ -273,8 +271,6 @@ void main(unsigned long bist)
}
#endif
post_code(0x3f);
-#if CONFIG_CHROMEOS
- init_chromeos(boot_mode);
-#endif
+ init_trusted_platform(boot_mode);
timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c
index bf6d428..4bdda85 100644
--- a/src/mainboard/google/link/chromeos.c
+++ b/src/mainboard/google/link/chromeos.c
@@ -18,7 +18,7 @@
*/
#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
+#include <bootmode.h>
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 66d2067..f4fd09e 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -40,9 +40,7 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include "gpio.h"
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
+#include <bootmode.h>
#include <cbfs.h>
#include <southbridge/intel/bd82x6x/chip.h>
@@ -317,8 +315,6 @@ void main(unsigned long bist)
}
#endif
post_code(0x3f);
-#if CONFIG_CHROMEOS
- init_chromeos(boot_mode);
-#endif
+ init_trusted_platform(boot_mode);
timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c
index fcf6374..be45735 100644
--- a/src/mainboard/google/parrot/chromeos.c
+++ b/src/mainboard/google/parrot/chromeos.c
@@ -19,7 +19,7 @@
#include <console/console.h>
#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
+#include <bootmode.h>
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 361c19b..7cf1055 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -38,9 +38,7 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include "gpio.h"
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
+#include <bootmode.h>
#include <cbfs.h>
#include "ec/compal/ene932/ec.h"
@@ -273,8 +271,6 @@ void main(unsigned long bist)
}
#endif
post_code(0x3f);
-#if CONFIG_CHROMEOS
- init_chromeos(boot_mode);
-#endif
+ init_trusted_platform(boot_mode);
timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/google/pit/chromeos.c b/src/mainboard/google/pit/chromeos.c
index 08b4e99..42ffe44 100644
--- a/src/mainboard/google/pit/chromeos.c
+++ b/src/mainboard/google/pit/chromeos.c
@@ -22,7 +22,7 @@
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
+#include <bootmode.h>
#include <cpu/samsung/exynos5420/cpu.h>
#include <cpu/samsung/exynos5420/gpio.h>
diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c
index c525a81..0e88ef2 100644
--- a/src/mainboard/google/snow/chromeos.c
+++ b/src/mainboard/google/snow/chromeos.c
@@ -22,7 +22,7 @@
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
+#include <bootmode.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/gpio.h>
diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c
index 62d5891..d600aec 100644
--- a/src/mainboard/google/stout/acpi_tables.c
+++ b/src/mainboard/google/stout/acpi_tables.c
@@ -31,7 +31,7 @@
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <vendorcode/google/chromeos/gnvs.h>
-#include <vendorcode/google/chromeos/chromeos.h>
+#include <bootmode.h>
#include <ec/quanta/it8518/ec.h>
#include "ec.h"
#include "onboard.h"
diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c
index 74955de..2032c05 100644
--- a/src/mainboard/google/stout/chromeos.c
+++ b/src/mainboard/google/stout/chromeos.c
@@ -18,7 +18,7 @@
*/
#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
+#include <bootmode.h>
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index f53c07d..011ff7d 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -39,9 +39,6 @@
#include <cpu/x86/msr.h>
#include "gpio.h"
#include <bootmode.h>
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
#include <cbfs.h>
#include <ec/quanta/it8518/ec.h>
#include "ec.h"
@@ -327,8 +324,6 @@ void main(unsigned long bist)
}
#endif
post_code(0x3f);
-#if CONFIG_CHROMEOS
- init_chromeos(boot_mode);
-#endif
+ init_trusted_platform(boot_mode);
timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c
index 72adaf7..bc99667 100644
--- a/src/mainboard/intel/emeraldlake2/chromeos.c
+++ b/src/mainboard/intel/emeraldlake2/chromeos.c
@@ -18,7 +18,7 @@
*/
#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
+#include <bootmode.h>
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 9308e96..93c02de 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -38,9 +38,7 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include "gpio.h"
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
+#include <bootmode.h>
#define SIO_PORT 0x164e
@@ -325,8 +323,6 @@ void main(unsigned long bist)
}
#endif
post_code(0x3f);
-#if CONFIG_CHROMEOS
- init_chromeos(boot_mode);
-#endif
+ init_trusted_platform(boot_mode);
timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index ef5a836..1882efe 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -45,9 +45,6 @@
#include "superio/smsc/lpc47n207/lpc47n207.h"
#include "superio/smsc/lpc47n207/early_serial.c"
#endif
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
static void pch_enable_lpc(void)
{
@@ -345,8 +342,6 @@ void main(unsigned long bist)
}
#endif
post_code(0x3f);
-#if CONFIG_CHROMEOS
- init_chromeos(boot_mode);
-#endif
+ init_trusted_platform(boot_mode);
timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 8d2a3e4..6e7b05e 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -45,9 +45,6 @@
#include "superio/smsc/lpc47n207/lpc47n207.h"
#include "superio/smsc/lpc47n207/early_serial.c"
#endif
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
/* Stumpy USB Reset Disable defined in cmos.layout */
#if CONFIG_USE_OPTION_TABLE
@@ -352,8 +349,6 @@ void main(unsigned long bist)
}
#endif
post_code(0x3f);
-#if CONFIG_CHROMEOS
- init_chromeos(boot_mode);
-#endif
+ init_trusted_platform(boot_mode);
timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index a1a9d9a..6c074c7 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -124,13 +124,5 @@ config VBOOT_REFCODE_INDEX
This is the index of the reference code component in the verified
firmware block.
-config NO_TPM_RESUME
- bool
- default n
- help
- On some boards the TPM stays powered up in S3. On those
- boards, booting Windows will break if the TPM resume command
- is sent during an S3 resume.
-
endif
endmenu
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index dc34dc3..acb2052 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -32,7 +32,7 @@ void read_vbnv(uint8_t *vbnv_copy);
void save_vbnv(const uint8_t *vbnv_copy);
/* functions implemented in vboot.c */
-void init_chromeos(int bootmode);
+void init_vboot(int bootmode);
#if CONFIG_VBOOT_VERIFY_FIRMWARE
/* Returns 0 on success < 0 on error. */
diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c
index 03d759c..58f96bd 100644
--- a/src/vendorcode/google/chromeos/vboot.c
+++ b/src/vendorcode/google/chromeos/vboot.c
@@ -25,7 +25,6 @@
#include "chromeos.h"
//#define EXTRA_LOGGING
-#define UBOOT_DOES_TPM_STARTUP
#define TPM_LARGE_ENOUGH_COMMAND_SIZE 256 /* saves space in the firmware */
@@ -39,11 +38,6 @@
#define TPM_E_NEEDS_SELFTEST ((u32)(TPM_E_NON_FATAL + 1))
#define TPM_E_DOING_SELFTEST ((u32)(TPM_E_NON_FATAL + 2))
-#if CONFIG_NO_TPM_RESUME
-static void init_vboot(int bootmode)
-{
-}
-#else
static const struct {
u8 buffer[12];
} tpm_resume_cmd = {
@@ -182,21 +176,11 @@ static u32 TlclSendReceive(const u8 * request, u8 * response, int max_length)
return result;
}
-static void init_vboot(int bootmode)
+void init_vboot(int bootmode)
{
u32 result;
u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE];
-#ifdef UBOOT_DOES_TPM_STARTUP
- /* Doing TPM startup when we're not coming in on the S3 resume path
- * saves us roughly 20ms in boot time only. This does not seem to
- * be worth an API change to vboot_reference-firmware right now, so
- * let's keep the code around, but just bail out early:
- */
- if (bootmode != 2)
- return;
-#endif
-
printk(BIOS_DEBUG, "Verified boot TPM initialization.\n");
printk(BIOS_SPEW, "TPM: Init\n");
@@ -236,9 +220,3 @@ static void init_vboot(int bootmode)
hard_reset();
#endif
}
-#endif
-
-void init_chromeos(int bootmode)
-{
- init_vboot(bootmode);
-}
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