[coreboot-gerrit] Patch set updated for coreboot: 1726628 baytrail: add more irq defintions
Aaron Durbin (adurbin@google.com)
gerrit at coreboot.org
Tue May 6 01:02:03 CEST 2014
Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4947
-gerrit
commit 172662861db4aedb4b9d54b433b274b1ea32e2ed
Author: Aaron Durbin <adurbin at chromium.org>
Date: Thu Nov 7 10:47:01 2013 -0600
baytrail: add more irq defintions
The IRQs used for devices that are in acpi mode are added as well
as the IRQ defitions for the dedicated GPIO IRQ routing.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built.
Change-Id: I2eed5a4584e2d908c32617c9289a2abeaa30bd44
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176120
Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
src/soc/intel/baytrail/baytrail/irq.h | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/src/soc/intel/baytrail/baytrail/irq.h b/src/soc/intel/baytrail/baytrail/irq.h
index 6461878..2359d21 100644
--- a/src/soc/intel/baytrail/baytrail/irq.h
+++ b/src/soc/intel/baytrail/baytrail/irq.h
@@ -28,7 +28,33 @@
#define PIRQF_APIC_IRQ 21
#define PIRQG_APIC_IRQ 22
#define PIRQH_APIC_IRQ 23
+/* The below IRQs are for when devices are in ACPI mode. Active low. */
+#define LPE_DMA0_IRQ 24
+#define LPE_DMA1_IRQ 25
+#define LPE_SSP0_IRQ 26
+#define LPE_SSP1_IRQ 27
+#define LPE_SSP2_IRQ 28
+#define LPE_IPC2HOST_IRQ 29
+#define LPSS_I2C1_IRQ 32
+#define LPSS_I2C2_IRQ 33
+#define LPSS_I2C3_IRQ 34
+#define LPSS_I2C4_IRQ 35
+#define LPSS_I2C5_IRQ 36
+#define LPSS_I2C6_IRQ 37
+#define LPSS_I2C7_IRQ 38
+#define LPSS_HSUART1_IRQ 39
+#define LPSS_HSUART2_IRQ 40
+#define LPSS_SPI_IRQ 41
+#define LPSS_DMA2_IRQ 42
+#define LPSS_DMA1_IRQ 43
+#define SCC_EMMC_IRQ 45
+#define SCC_SDIO_IRQ 46
+#define SCC_SD_IRQ 47
+/* The dedicated gpio irqs are active high. */
+#define GPIO_S0_DED_IRQ(slot) (51 + (slot))
+#define GPIO_S5_DED_IRQ(slot) (67 + (slot))
+/* PIC IRQ settings. */
#define PIRQ_PIC_IRQDISABLE 0x0
#define PIRQ_PIC_IRQ3 0x3
#define PIRQ_PIC_IRQ4 0x4
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