[coreboot-gerrit] Patch set updated for coreboot: dce18d3 mainboard/jetway/nf81-t56n-lf: Drop mptable.c

Edward O'Callaghan (eocallaghan@alterapraxis.com) gerrit at coreboot.org
Tue May 6 18:33:31 CEST 2014


Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5664

-gerrit

commit dce18d33de7a6d6aa984e3f9a1c019bf86199c59
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Tue May 6 03:29:33 2014 +1000

    mainboard/jetway/nf81-t56n-lf: Drop mptable.c
    
    mptable.c overrides coreboot's weak functions that derive this
    information from the devicetree.cb. Use coreboot-proper implementation
    in-place of hardcoded and probably invalid mptable.c implementation.
    
    We disable MPTables generation from the devicetree.cb for the moment
    since the required information is not currently defined for each PCI
    device. Also, there are few users of MPTables so it is not essential to
    support currently.
    
    Change-Id: I1a99f37b5e8821bb2aee46cf13f6caa1b05dbec1
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/mainboard/jetway/nf81-t56n-lf/Kconfig   |   3 +-
 src/mainboard/jetway/nf81-t56n-lf/mptable.c | 162 ----------------------------
 2 files changed, 2 insertions(+), 163 deletions(-)

diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
index 0f85386..32281ef 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig
+++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
@@ -28,7 +28,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SUPERIO_FINTEK_F71869AD
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
+#	To auto-generate MP_Tables interrupts need to be defined in devicetree.cb
+#	select HAVE_MP_TABLE
 	select HAVE_ACPI_RESUME
 	select SERIAL_CPU_INIT
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
deleted file mode 100644
index 9be4854..0000000
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#include <arch/io.h>
-#include <arch/smp/mpspec.h>
-#include <console/console.h>
-#include <cpu/amd/amdfam14.h>
-#include <device/pci.h>
-#include <stdint.h>
-#include <string.h>
-
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-extern u8 bus_sb800[6];
-
-extern u32 apicid_sb800;
-
-extern u32 bus_type[256];
-extern u32 sbdn_sb800;
-
-u8 intr_data[] = {
-	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
-	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
-	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x10,0x11,0x12,0x13
-};
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-	memcpy(mc->mpc_oem, "JETWAY	 ", 8);
-
-	smp_write_processors(mc);
-
-	get_bus_conf();
-
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/* I/O APICs:	 APIC ID Version State	 Address */
-
-	u32 dword;
-	u8 byte;
-
-	ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
-	dword &= 0xFFFFFFF0;
-	smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
-	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
-	outb(byte | 0x80, 0xC00);
-	outb(intr_data[byte], 0xC01);
-	}
-
-	/* I/O Ints:	Type	Polarity	Trigger	 Bus ID	 IRQ	APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
-	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
-
-	/* PCI interrupts are level triggered, and are
-	 * associated with a specific bus/device/function tuple.
-	 */
-#if !CONFIG_GENERATE_ACPI_TABLES
-#define PCI_INT(bus, dev, fn, pin) \
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
-#else
-#define PCI_INT(bus, dev, fn, pin)
-#endif
-
-	/* APU Internal Graphic Device*/
-	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
-	PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
-
-	PCI_INT(0x0, 0x14, 0x0, 0x10);
-	/* Southbridge HD Audio: */
-	PCI_INT(0x0, 0x14, 0x2, 0x12);
-
-	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
-	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
-	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
-	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
-	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
-	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
-
-	/* SATA */
-	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
-
-	/* On-board NIC & Slot PCIE. */
-
-	/* PCI slots */
-	/* PCI_SLOT 0. */
-	PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
-	PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
-	PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
-	PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
-	/* On-board Realtek NIC 1. */
-	PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
-	PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
-	PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
-	PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
-	/* PCI_SLOT 2. */
-	PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
-	PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
-	PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
-	PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
-	PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
-	PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
-	PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
-
-	/* On-board Realtek NIC 2. (PCIe PortA) */
-	PCI_INT(0x0, 0x15, 0x0, 0x10);
-	/* PCIe PortB */
-	PCI_INT(0x0, 0x15, 0x1, 0x11);
-	/* PCIe PortC */
-	PCI_INT(0x0, 0x15, 0x2, 0x12);
-	/* PCIe PortD */
-	PCI_INT(0x0, 0x15, 0x3, 0x13);
-
-	/* Local Ints:
-	 * Type | Polarity | Trigger | Bus ID | IRQ | APIC ID PIN#
-	 */
-	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
-	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}



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