[coreboot-gerrit] Patch merged into coreboot/master: 59a4cd5 baytrail: add support for routing gpio pins to smi/sci
gerrit at coreboot.org
gerrit at coreboot.org
Tue May 6 18:39:25 CEST 2014
the following patch was just integrated into master:
commit 59a4cd55782f1148d37f0c2408657ba93deefc86
Author: Aaron Durbin <adurbin at chromium.org>
Date: Mon Nov 11 12:09:28 2013 -0600
baytrail: add support for routing gpio pins to smi/sci
In order for gpio pins to trigger an smi/sci the GPIO_ROUT
register needs to be set accordingly. For SMI, the ALT_GPIO_SMI
register needs to be enabled for each gpio as well.
The first 8 gpios from the suspend and core well are the only gpios
that can trigger an SMI or SCI. The settings for the GPIO_ROUT
and ALT_GPIO_SMI register are not commited until the SMM settings
are enabled in the southcluster.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Manually triggered SCI by changing GPE0a_EN
and toggling PCH_WAKE_L on the EC console.
Change-Id: Id79b70084edc39fc047475e984494c224bd75d6d
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176390
Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
Reviewed-on: http://review.coreboot.org/4957
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
See http://review.coreboot.org/4957 for details.
-gerrit
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