[coreboot-gerrit] Patch set updated for coreboot: b76f17a baytrail: initialize common SSC functionality
Aaron Durbin (adurbin@google.com)
gerrit at coreboot.org
Tue May 6 18:41:42 CEST 2014
Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4966
-gerrit
commit b76f17ad99f0d0510d79a1bc5a2c2a73edd6d787
Author: Aaron Durbin <adurbin at chromium.org>
Date: Tue Nov 12 16:40:33 2013 -0600
baytrail: initialize common SSC functionality
The SSC (storage control cluster) houses the SD, SDIO, and eMMC
interfaces. The scc cofniguration function, baytrail_init_scc(),
is ran in the pre device stage to initialize the SCC. The eMMC
is expected to be configured for version 4.5.
BUG=chrome-os-partner:23966
BRANCH=None
TEST=Built and booted with some other eMMC changes into login screen off
of eMMC device.
Change-Id: I81cc755a790b7e43ad234a8201dae480277202c8
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176535
Reviewed-by: Bernie Thompson <bhthompson at chromium.org>
Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
src/soc/intel/baytrail/Makefile.inc | 1 +
src/soc/intel/baytrail/baytrail/ramstage.h | 1 +
src/soc/intel/baytrail/ramstage.c | 2 +
src/soc/intel/baytrail/scc.c | 83 ++++++++++++++++++++++++++++++
4 files changed, 87 insertions(+)
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 81b2c24..c7e3843 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -39,6 +39,7 @@ ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
ramstage-y += sata.c
ramstage-y += acpi.c
ramstage-y += lpe.c
+ramstage-y += scc.c
# Remove as ramstage gets fleshed out
ramstage-y += placeholders.c
diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h
index 4fa6ddd..217c67b 100644
--- a/src/soc/intel/baytrail/baytrail/ramstage.h
+++ b/src/soc/intel/baytrail/baytrail/ramstage.h
@@ -33,6 +33,7 @@ void baytrail_run_reference_code(void);
#else
static inline void baytrail_run_reference_code(void) {}
#endif
+void baytrail_init_scc(void);
extern struct pci_operations soc_pci_ops;
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 0c2bed8..b0b48b0 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -166,6 +166,8 @@ void baytrail_init_pre_device(void)
config = mainboard_get_gpios();
setup_soc_gpios(config);
+ baytrail_init_scc();
+
/* Indicate S3 resume to rest of ramstage. */
s3_resume_prepare();
}
diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c
new file mode 100644
index 0000000..af941fa
--- /dev/null
+++ b/src/soc/intel/baytrail/scc.c
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <reg_script.h>
+
+#include <baytrail/iosf.h>
+#include <baytrail/ramstage.h>
+
+static const struct reg_script scc_start_dll[] = {
+ /* Configure master DLL. */
+ REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4964, 0x00078000),
+ /* Configure Swing,FSM for Master DLL */
+ REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00000133),
+ /* Run+Local Reset on Master DLL */
+ REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00001933),
+ REG_SCRIPT_END,
+};
+
+static const struct reg_script scc_after_dll[] = {
+ /* Configure Write Path */
+ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4954, ~0x7fff, 0x35ad),
+ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4958, ~0x7fff, 0x35ad),
+ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x495c, ~0x7fff, 0x35ad),
+ /* Configure Read Path */
+ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x43e4, ~0x7fff, 0x35ad),
+ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4324, ~0x7fff, 0x35ad),
+ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x42b4, ~0x7fff, 0x35ad),
+ /* eMMC 4.5 TX and RX DLL */
+ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a4, ~0x1f001f, 0xa000d),
+ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a8, ~0x1f001f, 0xd000d),
+ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49ac, ~0x1f001f, 0xd000d),
+ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b0, ~0x1f001f, 0xd000d),
+ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b4, ~0x1f001f, 0xd000d),
+ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b8, ~0x1, 0x0),
+ /* cfio_regs_mmc1_ELECTRICAL.nslew/pslew */
+ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x0),
+ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x0),
+ /*
+ * iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_ocp = 01
+ * iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_xin = 01
+ */
+ REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0xf, 0x5),
+ /* Enable IOSF Snoop */
+ REG_IOSF_OR(IOSF_PORT_SCC, 0x00, (1 << 7)),
+ /* SDIO 3V Support. */
+ REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0x30, 0x30),
+ REG_SCRIPT_END,
+};
+
+void baytrail_init_scc(void)
+{
+ uint32_t dll_values;
+
+ printk(BIOS_DEBUG, "Initializing sideband SCC registers.\n");
+
+ /* Common Sideband Initialization for SCC */
+ reg_script_run(scc_start_dll);
+
+ /* Override Slave Path - populate DLL settings. */
+ dll_values = iosf_score_read(0x496c) & 0x7ffff;
+ dll_values |= iosf_score_read(0x4950) & ~0xfffff;
+ iosf_score_write(0x4950, dll_values | (1 << 19));
+
+ reg_script_run(scc_after_dll);
+}
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