[coreboot-gerrit] Patch merged into coreboot/master: dc866cf baytrail: first pass at lpss device initialization
gerrit at coreboot.org
gerrit at coreboot.org
Wed May 7 12:05:13 CEST 2014
the following patch was just integrated into master:
commit dc866cff31e26de7cf95bbd0675037d8066f7dc8
Author: Aaron Durbin <adurbin at chromium.org>
Date: Tue Nov 12 20:21:53 2013 -0600
baytrail: first pass at lpss device initialization
This commit does the common parts for all LPSS devices
that are enabled: enable snoop in IOSF and enable power
management. Additionally, the i2c devices are taken out of
reset.
BUG=chrome-os-partner:23790
BRANCH=None
TEST=Built and booted with modified kernel-next. I2C bus devices
show up and I see 0x10 on one of the buses.
Change-Id: I540caea6a8666f5684dc5cee683a6b085dfac6de
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176424
Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
Reviewed-on: http://review.coreboot.org/4969
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick at georgi-clan.de>
See http://review.coreboot.org/4969 for details.
-gerrit
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