[coreboot-gerrit] Patch set updated for coreboot: 2e583d1 baytrail: enable caching and prefetching in spi controller

Aaron Durbin (adurbin@google.com) gerrit at coreboot.org
Wed May 7 17:11:05 CEST 2014


Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4976

-gerrit

commit 2e583d1c4614c062e043a93412f341998d4382be
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Nov 18 11:16:20 2013 -0600

    baytrail: enable caching and prefetching in spi controller
    
    The default mode of the SPI controller has prefetching disabled.
    That obviously has a performance impact. Enable both caching
    and prefetching to make booting faster. This has a significant
    impact on streaming data out of SPI.
    
    BUG=chrome-os-partner:24085
    BRANCH=None
    TEST=Built and booted rambi. Payload loading step went from ~285ms
         to ~54ms.
    
    Change-Id: I065cf44e1de7dcefc49aa9ea9ad0204929ab26f4
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/177220
    Reviewed-by: Shawn Nematbakhsh <shawnn at chromium.org>
---
 src/soc/intel/baytrail/baytrail/spi.h      | 31 ++++++++++++++++++++++++++++++
 src/soc/intel/baytrail/romstage/romstage.c | 10 ++++++++++
 2 files changed, 41 insertions(+)

diff --git a/src/soc/intel/baytrail/baytrail/spi.h b/src/soc/intel/baytrail/baytrail/spi.h
new file mode 100644
index 0000000..abe9e14
--- /dev/null
+++ b/src/soc/intel/baytrail/baytrail/spi.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BAYTRAIL_SPI_H_
+#define _BAYTRAIL_SPI_H_
+
+/* These registers live behind SPI_BASE_ADDRESS. */
+#define BCR				0xfc
+# define SRC_MASK			(0x3 << 2)
+# define SRC_CACHE_NO_PREFETCH		(0x0 << 2)
+# define SRC_NO_CACHE_NO_PREFETCH	(0x1 << 2)
+# define SRC_CACHE_PREFETCH		(0x2 << 2)
+
+#endif /* _BAYTRAIL_SPI_H_ */
+
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 91637d5..8436c65 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -41,6 +41,7 @@
 #include <baytrail/reset.h>
 #include <baytrail/romstage.h>
 #include <baytrail/smm.h>
+#include <baytrail/spi.h>
 
 static inline uint64_t timestamp_get(void)
 {
@@ -94,6 +95,13 @@ static void program_base_addresses(void)
 	pci_write_config32(lpc_dev, GBASE, reg);
 }
 
+static void spi_init(void)
+{
+	const unsigned long bcr = SPI_BASE_ADDRESS + BCR;
+	/* Enable caching and prefetching in the SPI controller. */
+	write32(bcr, (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH);
+}
+
 static inline void mark_ts(struct romstage_params *rp, uint64_t ts)
 {
 	struct romstage_timestamps *rt = &rp->ts;
@@ -124,6 +132,8 @@ void * asmlinkage romstage_main(unsigned long bist,
 
 	console_init();
 
+	spi_init();
+
 	set_max_freq();
 
 	punit_init();



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