[coreboot-gerrit] Patch set updated for coreboot: 072e17a rambi: configure the LPE audio codec clock
Aaron Durbin (adurbin@google.com)
gerrit at coreboot.org
Wed May 7 22:15:30 CEST 2014
Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4987
-gerrit
commit 072e17a559c5ab283fae8cd2a44a1a3380ed7636
Author: Aaron Durbin <adurbin at chromium.org>
Date: Wed Dec 4 11:29:46 2013 -0600
rambi: configure the LPE audio codec clock
Rambi has the LPE audio codec connected to PMC_PLT_CLK[0].
Configure it for 25MHz.
BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted. Noted message in console output.
Change-Id: I11297ba951149e5831c65ca70ac7bdbbed113098
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178781
Reviewed-by: Shawn Nematbakhsh <shawnn at chromium.org>
---
src/mainboard/google/rambi/devicetree.cb | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index 88785c0..1c24d57 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -23,6 +23,10 @@ chip soc/intel/baytrail
register "usb2_per_port_lane3" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+ # LPE audio codec settings
+ register "lpe_codec_clk_freq" = "25" # 25MHz clock
+ register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
+
device cpu_cluster 0 on
device lapic 0 on end
end
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