[coreboot-gerrit] New patch to review for coreboot: d8a97e6 gizmosphere/gizmo/mptable.c: Properly indent with GNU indent 2.2.11
Paul Menzel (paulepanter@users.sourceforge.net)
gerrit at coreboot.org
Thu May 8 08:56:14 CEST 2014
Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5694
-gerrit
commit d8a97e6283a49baec9f2f926820401f51a33cf52
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date: Thu May 8 08:04:44 2014 +0200
gizmosphere/gizmo/mptable.c: Properly indent with GNU indent 2.2.11
$ indent -linux src/mainboard/gizmosphere/gizmo/mptable.c
Change-Id: I69ea5b7cd28aadee104d5df8fc3b7e6c88c4ea2a
Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
src/mainboard/gizmosphere/gizmo/mptable.c | 34 +++++++++++++++++--------------
1 file changed, 19 insertions(+), 15 deletions(-)
diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c
index 6dfd11d..cc9e627 100755
--- a/src/mainboard/gizmosphere/gizmo/mptable.c
+++ b/src/mainboard/gizmosphere/gizmo/mptable.c
@@ -18,7 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
#include <console/console.h>
#include <arch/smp/mpspec.h>
#include <device/pci.h>
@@ -36,13 +35,18 @@ extern u32 bus_type[256];
extern u32 sbdn_sb800;
u8 intr_data[] = {
- [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
- [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
- [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
+ [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */
+ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
+ [0x10] =
+ 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
};
static void *smp_write_config_table(void *v)
@@ -61,7 +65,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */
+ /* I/O APICs: APIC ID Version State Address */
u32 dword;
u8 byte;
@@ -70,12 +74,12 @@ static void *smp_write_config_table(void *v)
dword &= 0xFFFFFFF0;
smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ for (byte = 0x0; byte < sizeof(intr_data); byte++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -91,7 +95,7 @@ static void *smp_write_config_table(void *v)
#define PCI_INT(bus, dev, fn, pin)
#endif
- /* APU Internal Graphic Device*/
+ /* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
@@ -100,7 +104,7 @@ static void *smp_write_config_table(void *v)
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
+ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
@@ -110,7 +114,7 @@ static void *smp_write_config_table(void *v)
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
- /* on board NIC & Slot PCIE. */
+ /* on board NIC & Slot PCIE. */
/* PCI slots */
/* PCI_SLOT 0. */
@@ -144,7 +148,7 @@ static void *smp_write_config_table(void *v)
/* PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
More information about the coreboot-gerrit
mailing list