[coreboot-gerrit] Patch set updated for coreboot: 4649891 rambi: Enable DPTF

Aaron Durbin (adurbin@google.com) gerrit at coreboot.org
Thu May 8 17:06:32 CEST 2014


Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5003

-gerrit

commit 4649891d1522f71b416ba87c03288b1e7fec0ac7
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Dec 10 07:48:00 2013 -0800

    rambi: Enable DPTF
    
    This enables the DPTF framework, but it doesn't do much
    without some sort of kernel+user components to drive it.
    
    BUG=chrome-os-partner:17279
    BRANCH=none
    TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF
    
    Change-Id: Icb632a6e70c3912bbdfa6ef3f5c87cd79d2b8a3a
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179480
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/rambi/acpi/dptf.asl | 28 +++++++++++++++++++++++++
 src/mainboard/google/rambi/acpi_tables.c |  8 ++++++++
 src/mainboard/google/rambi/dsdt.asl      |  3 +++
 src/mainboard/google/rambi/thermal.h     | 35 +++++---------------------------
 4 files changed, 44 insertions(+), 30 deletions(-)

diff --git a/src/mainboard/google/rambi/acpi/dptf.asl b/src/mainboard/google/rambi/acpi/dptf.asl
new file mode 100644
index 0000000..0d5cd65
--- /dev/null
+++ b/src/mainboard/google/rambi/acpi/dptf.asl
@@ -0,0 +1,28 @@
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TCPU, 100, 50, 0, 0, 0, 0},
+
+	/* CPU and Charger Effect on Temp Sensor 0 */
+	Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 50, 0, 0, 0, 0 },
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 80, 300, 0, 0, 0, 0 },
+
+	/* CPU and Charger Effect on Temp Sensor 1 */
+	Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 50, 0, 0, 0, 0 },
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 80, 300, 0, 0, 0, 0 },
+
+	/* CPU and Charger Effect on Temp Sensor 2 */
+	Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 50, 0, 0, 0, 0 },
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 80, 300, 0, 0, 0, 0 },
+})
+
+/* Include Baytrail DPTF */
+#include <soc/intel/baytrail/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c
index a4754f1..1d96dec 100644
--- a/src/mainboard/google/rambi/acpi_tables.c
+++ b/src/mainboard/google/rambi/acpi_tables.c
@@ -36,6 +36,8 @@
 #include <baytrail/nvs.h>
 #include <baytrail/iomap.h>
 
+#include "thermal.h"
+
 extern const unsigned char AmlCode[];
 
 static void acpi_create_gnvs(global_nvs_t *gnvs)
@@ -59,6 +61,12 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
 	/* TPM Present */
 	gnvs->tpmp = 1;
 
+	/* Enable DPTF */
+	gnvs->tcrt = CRITICAL_TEMPERATURE;
+	gnvs->tpsv = PASSIVE_TEMPERATURE;
+	gnvs->tact = ACTIVE_TEMPERATURE;
+	gnvs->dpte = 1;
+
 #if CONFIG_CHROMEOS
 	chromeos_init_vboot(&(gnvs->chromeos));
 	gnvs->chromeos.vbt2 = google_ec_running_ro() ?
diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl
index 1fbb8eb..53f2922 100644
--- a/src/mainboard/google/rambi/dsdt.asl
+++ b/src/mainboard/google/rambi/dsdt.asl
@@ -46,6 +46,9 @@ DefinitionBlock(
 			//#include <soc/intel/baytrail/acpi/northcluster.asl>
 			#include <soc/intel/baytrail/acpi/southcluster.asl>
 		}
+
+		/* Dynamic Platform Thermal Framework */
+		#include "acpi/dptf.asl"
 	}
 
 	#include "acpi/chromeos.asl"
diff --git a/src/mainboard/google/rambi/thermal.h b/src/mainboard/google/rambi/thermal.h
index f771014..2432b8d 100644
--- a/src/mainboard/google/rambi/thermal.h
+++ b/src/mainboard/google/rambi/thermal.h
@@ -20,38 +20,13 @@
 #ifndef BAYLEYBAY_THERMAL_H
 #define BAYLEYBAY_THERMAL_H
 
-/* Fan is OFF */
-#define FAN4_THRESHOLD_OFF	0
-#define FAN4_THRESHOLD_ON	0
-#define FAN4_PWM		0x00
-
-/* Fan is at LOW speed */
-#define FAN3_THRESHOLD_OFF	48
-#define FAN3_THRESHOLD_ON	55
-#define FAN3_PWM		0x40
-
-/* Fan is at MEDIUM speed */
-#define FAN2_THRESHOLD_OFF	52
-#define FAN2_THRESHOLD_ON	64
-#define FAN2_PWM		0x80
-
-/* Fan is at HIGH speed */
-#define FAN1_THRESHOLD_OFF	60
-#define FAN1_THRESHOLD_ON	68
-#define FAN1_PWM		0xb0
-
-/* Fan is at FULL speed */
-#define FAN0_THRESHOLD_OFF	66
-#define FAN0_THRESHOLD_ON	78
-#define FAN0_PWM		0xff
-
 /* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE	100
+#define CRITICAL_TEMPERATURE	95
 
-/* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE	90
+/* Passive cooling policy threshold */
+#define PASSIVE_TEMPERATURE	0
 
-/* Tj_max value for calculating PECI CPU temperature */
-#define MAX_TEMPERATURE		100
+/* Temperature which OS will throttle CPU (when using a Fan) */
+#define ACTIVE_TEMPERATURE	80
 
 #endif



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