[coreboot-gerrit] Patch merged into coreboot/master: 7538937 rambi: export SPI write-protect GPIO correctly
gerrit at coreboot.org
gerrit at coreboot.org
Fri May 9 05:41:32 CEST 2014
the following patch was just integrated into master:
commit 7538937d6e7c474dc7c17a1bc3c3591f0e6ef311
Author: Aaron Durbin <adurbin at chromium.org>
Date: Mon Dec 9 13:41:32 2013 -0600
rambi: export SPI write-protect GPIO correctly
Bay Trail has 3 banks of gpios. Therefore, in order to
properly identify a gpio the specific bank number as well
as the GPIO within that bank is needed. The SPI
write-protect GPIO is GPIO 6 within the SUS bank (offset
0x2000).
BUG=chrome-os-partner:24324
BUG=chrome-os-partner:24408
BRANCH=None
TEST=Built and booted. Looked at GPIO sysfs in the
chromeos_acpi directory.
Change-Id: Ic51b5abe3bacf6cf9b6a90cf666f1a63b098a0e3
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179195
Reviewed-on: http://review.coreboot.org/4995
Reviewed-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/4995 for details.
-gerrit
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