[coreboot-gerrit] Patch set updated for coreboot: 69b21ff rambi: Disable HSUART2 and SPI interfaces

Aaron Durbin (adurbin@google.com) gerrit at coreboot.org
Mon May 12 16:41:01 CEST 2014


Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5020

-gerrit

commit 69b21ffe6e4e5e9036e2200dd599c97e2a1a6a1b
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Dec 13 16:01:56 2013 -0800

    rambi: Disable HSUART2 and SPI interfaces
    
    Not used currently on rambi board.  Disable in case it
    saves power.
    
    BUG=chrome-os-partner:23862
    BRANCH=none
    TEST=build and boot on rambi
    
    Change-Id: Idb870c2cfa88cb6c3f1ada3caf0db566e33ec1eb
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/180084
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/rambi/devicetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index bfb9e30..fe5ec7b 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -75,8 +75,8 @@ chip soc/intel/baytrail
 		device pci 1e.1 off end # PWM1
 		device pci 1e.2 off end # PWM2
 		device pci 1e.3 off end # HSUART1
-		device pci 1e.4 on  end # HSUART2
-		device pci 1e.5 on  end # SPI
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
 		device pci 1f.0 on
 			chip ec/google/chromeec
 				# We only have one init function that



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