[coreboot-gerrit] Patch set updated for coreboot: 5d70768 rambi: dptf: Set critical thresholds
Aaron Durbin (adurbin@google.com)
gerrit at coreboot.org
Tue May 13 16:29:11 CEST 2014
Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5038
-gerrit
commit 5d707684952d27feccd987ba40427e861fb04909
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Thu Jan 9 10:10:51 2014 -0800
rambi: dptf: Set critical thresholds
Set critical temperature thresdholds to 70C. This will cause DPTF
framework to shut down the system so it may need to be higher or
lower but will need some testing.
BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi, start DPTF framework and observe it
using specified critical thresholds.
Change-Id: Ibbf6d814295eb5ff006cb879676b7613f5eb56a3
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182025
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/rambi/acpi/dptf.asl | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/google/rambi/acpi/dptf.asl b/src/mainboard/google/rambi/acpi/dptf.asl
index 8dca454..afb20de 100644
--- a/src/mainboard/google/rambi/acpi/dptf.asl
+++ b/src/mainboard/google/rambi/acpi/dptf.asl
@@ -1,28 +1,31 @@
#define DPTF_TSR0_SENSOR_ID 1
#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
#define DPTF_TSR0_PASSIVE 40
+#define DPTF_TSR0_CRITICAL 70
#define DPTF_TSR1_SENSOR_ID 2
#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
#define DPTF_TSR1_PASSIVE 45
+#define DPTF_TSR1_CRITICAL 70
#define DPTF_TSR2_SENSOR_ID 3
#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
#define DPTF_TSR2_PASSIVE 35
+#define DPTF_TSR2_CRITICAL 70
#undef DPTF_ENABLE_CHARGER
Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */
- Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TCPU, 100, 50, 0, 0, 0, 0},
+ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TCPU, 100, 50, 0, 0, 0, 0 },
- /* CPU and Charger Effect on Temp Sensor 0 */
+ /* CPU Effect on Temp Sensor 0 */
Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 50, 0, 0, 0, 0 },
- /* CPU and Charger Effect on Temp Sensor 1 */
+ /* CPU Effect on Temp Sensor 1 */
Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 50, 0, 0, 0, 0 },
- /* CPU and Charger Effect on Temp Sensor 2 */
+ /* CPU Effect on Temp Sensor 2 */
Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 50, 0, 0, 0, 0 },
})
More information about the coreboot-gerrit
mailing list