[coreboot-gerrit] Patch set updated for coreboot: 1f4781d baytrail: Add ACPI Device for XHCI

Aaron Durbin (adurbin@google.com) gerrit at coreboot.org
Wed May 14 15:57:31 CEST 2014


Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5046

-gerrit

commit 1f4781d8e2d67069a2a95a44d30db2f744685ce4
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Jan 14 14:59:28 2014 -0800

    baytrail: Add ACPI Device for XHCI
    
    This will allow USB devices to wake the system (if 5V is not turned off)
    and the controller to enter D3 at runtime. (if autosuspend is enabled)
    
    BUG=chrome-os-partner:23629
    BRANCH=baytrail
    TEST=build and boot on baytrail
    
    1) with modified EC to leave 5V on in S3 ensure that waking from suspend
    with USB keyboard works.
    2) with laptop-mode-tools usb autosuepend config updated see that device
    enters D3 at runtime when no external devices attached.
    
    Change-Id: Ia396d42494e30105f06eb3bd65b4ba8b1372cf35
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182536
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/baytrail/acpi/southcluster.asl |  3 +++
 src/soc/intel/baytrail/acpi/xhci.asl         | 36 ++++++++++++++++++++++++++++
 2 files changed, 39 insertions(+)

diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index ced1618..61642a5 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -252,6 +252,9 @@ Device (IOSF)
 // LPC Bridge 0:1f.0
 #include "lpc.asl"
 
+// USB XHCI 0:14.0
+#include "xhci.asl"
+
 // IRQ routing for each PCI device
 #include "irqroute.asl"
 
diff --git a/src/soc/intel/baytrail/acpi/xhci.asl b/src/soc/intel/baytrail/acpi/xhci.asl
new file mode 100644
index 0000000..4d5367a
--- /dev/null
+++ b/src/soc/intel/baytrail/acpi/xhci.asl
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (XHCI)
+{
+	Name (_ADR, 0x00140000)
+	Name (_PRW, Package () { 0x0d, 3 })
+	Name (_S3D, 3) /* Highest D state in S3 state */
+
+	Device (RHUB)
+	{
+		Name (_ADR, 0x00000000)
+		Device (PRT1) { Name (_ADR, 1) }
+		Device (PRT2) { Name (_ADR, 2) }
+		Device (PRT3) { Name (_ADR, 3) }
+		Device (PRT4) { Name (_ADR, 4) }
+	}
+}



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