[coreboot-gerrit] Patch set updated for coreboot: 368c748 amd/agesa: Implicit assigment between enum without cast

Edward O'Callaghan (eocallaghan@alterapraxis.com) gerrit at coreboot.org
Mon May 19 20:53:17 CEST 2014


Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5760

-gerrit

commit 368c748cdcbd50480a452329e244b61712193455
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Thu May 15 21:23:51 2014 +1000

    amd/agesa: Implicit assigment between enum without cast
    
    Change-Id: I31632948ce69b2d1ff63b6c920016ed6fdf9e2f8
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c | 2 +-
 src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c | 2 +-
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c
index 2ad6e12..942fe1f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c
@@ -206,7 +206,7 @@ MemNSyncTargetSpeedNb (
           ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ?
             ((MEMORY_BUS_SPEED)ChnlTmgMod[1] >= DDR667_FREQUENCY) :
             ((MEMORY_BUS_SPEED)ChnlTmgMod[1] <= DDR1066_FREQUENCY));
-          MemClkFreq = ChnlTmgMod[1];
+          MemClkFreq = (MEMORY_BUS_SPEED) ChnlTmgMod[1];
         }
       }
 
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c
index eac35b7..3664dc5 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c
@@ -178,7 +178,7 @@ MemNSyncTargetSpeedNb (
 //          ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ?
 //            (ChnlTmgMod[1] >= DDR667_FREQUENCY) :
 //            (ChnlTmgMod[1] <= DDR1066_FREQUENCY));
-          MemClkFreq = ChnlTmgMod[1];
+          MemClkFreq = (MEMORY_BUS_SPEED) ChnlTmgMod[1];
         }
       }
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c
index 613aadd..9ff66f2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c
@@ -186,7 +186,7 @@ MemNSyncTargetSpeedNb (
           ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ?
             ((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) >= DDR667_FREQUENCY) :
             ((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) <= DDR1066_FREQUENCY));
-          MemClkFreq = ChnlTmgMod[1];
+          MemClkFreq = (MEMORY_BUS_SPEED) ChnlTmgMod[1];
         }
       }
 



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