[coreboot-gerrit] New patch to review for coreboot: b60faa0 northbridge/amd/amdmct/mct: Initialize variables at the eol
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Thu May 22 22:22:36 CEST 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5816
-gerrit
commit b60faa019bfec01185b2de4ae3e826232ebce23a
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Fri May 23 05:55:04 2014 +1000
northbridge/amd/amdmct/mct: Initialize variables at the eol
Spotted by Clang
Change-Id: Idada98b7863ef986021943cf3ddb92d2f035e3e1
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/northbridge/amd/amdmct/mct/mctndi_d.c | 2 +-
src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/amd/amdmct/mct/mctndi_d.c b/src/northbridge/amd/amdmct/mct/mctndi_d.c
index 1404355..a408d47 100644
--- a/src/northbridge/amd/amdmct/mct/mctndi_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctndi_d.c
@@ -27,7 +27,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat,
u8 Node;
u32 Base;
u32 MemSize, MemSize0 = 0;
- u32 Dct0MemSize = 0, DctSelBase, DctSelBaseOffset;
+ u32 Dct0MemSize, DctSelBase, DctSelBaseOffset = 0;
u8 Nodes;
u8 NodesWmem;
u8 DoIntlv;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c
index d3b2aad..520a178 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c
@@ -24,7 +24,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat,
u8 Node;
u32 Base;
u32 MemSize, MemSize0 = 0;
- u32 Dct0MemSize = 0, DctSelBase, DctSelBaseOffset;
+ u32 Dct0MemSize, DctSelBase, DctSelBaseOffset = 0;
u8 Nodes;
u8 NodesWmem;
u8 DoIntlv;
More information about the coreboot-gerrit
mailing list