[coreboot-gerrit] New patch to review for coreboot: f9acde4 mainboard/intel/wtm2: Fix usage of GNU field designator extension
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Fri May 23 18:13:17 CEST 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5825
-gerrit
commit f9acde41c453d7105a3dfeded17d9f895b96d551
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Sat May 24 02:06:10 2014 +1000
mainboard/intel/wtm2: Fix usage of GNU field designator extension
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
In C99 we defined a syntax for this. GCC's old syntax was deprecated.
Change-Id: I46fad8d236c620ee5dbeb24f4517f20f00db839f
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/mainboard/intel/wtm2/romstage.c | 44 ++++++++++++++++++-------------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c
index eacfb46..b831244 100644
--- a/src/mainboard/intel/wtm2/romstage.c
+++ b/src/mainboard/intel/wtm2/romstage.c
@@ -75,31 +75,31 @@ const struct rcba_config_instruction rcba_config[] = {
void mainboard_romstage_entry(unsigned long bist)
{
struct pei_data pei_data = {
- pei_version: PEI_VERSION,
- mchbar: DEFAULT_MCHBAR,
- dmibar: DEFAULT_DMIBAR,
- epbar: DEFAULT_EPBAR,
- pciexbar: DEFAULT_PCIEXBAR,
- smbusbar: SMBUS_IO_BASE,
- wdbbar: 0x4000000,
- wdbsize: 0x1000,
- hpet_address: HPET_ADDR,
- rcba: DEFAULT_RCBA,
- pmbase: DEFAULT_PMBASE,
- gpiobase: DEFAULT_GPIOBASE,
- temp_mmio_base: 0xfed08000,
- system_type: 5, /* ULT */
- tseg_size: CONFIG_SMM_TSEG_SIZE,
- spd_addresses: { 0xa2, 0x00, 0xa2, 0x00 },
- ec_present: 1,
+ .pei_version = PEI_VERSION,
+ .mchbar = DEFAULT_MCHBAR,
+ .dmibar = DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = DEFAULT_PCIEXBAR,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = HPET_ADDR,
+ .rcba = DEFAULT_RCBA,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .temp_mmio_base = 0xfed08000,
+ .system_type = 5, /* ULT */
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xa2, 0x00, 0xa2, 0x00 },
+ .ec_present = 1,
// 0 = leave channel enabled
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel
// 3 = disable dimm 0+1 on channel
- dimm_channel0_disabled: 2,
- dimm_channel1_disabled: 2,
- max_ddr3_freq: 1600,
- usb2_ports: {
+ .dimm_channel0_disabled = 2,
+ .dimm_channel1_disabled = 2,
+ .max_ddr3_freq = 1600,
+ .usb2_ports = {
/* Length, Enable, OCn# */
{ 0x40, 1, USB_OC_PIN_SKIP, /* P0: */
USB_PORT_FRONT_PANEL },
@@ -118,7 +118,7 @@ void mainboard_romstage_entry(unsigned long bist)
{ 0x40, 0, USB_OC_PIN_SKIP, /* P7: */
USB_PORT_FRONT_PANEL },
},
- usb3_ports: {
+ .usb3_ports = {
/* Enable, OCn# */
{ 1, USB_OC_PIN_SKIP }, /* P1; */
{ 1, USB_OC_PIN_SKIP }, /* P2; */
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