[coreboot-gerrit] New patch to review for coreboot: 3f16922 mainboard/intel/emeraldlake2 Fix usage of GNU field designator ext

Edward O'Callaghan (eocallaghan@alterapraxis.com) gerrit at coreboot.org
Fri May 23 18:13:19 CEST 2014


Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5827

-gerrit

commit 3f1692219b4a496d897ce10e1c74948d877bd222
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Sat May 24 02:08:04 2014 +1000

    mainboard/intel/emeraldlake2 Fix usage of GNU field designator ext
    
    Following the reasoning in,
    8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
    
    In C99 we defined a syntax for this. GCC's old syntax was deprecated.
    
    Change-Id: Idda1a49277c156670014fac27b9f1c378f8df0cd
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/mainboard/intel/emeraldlake2/romstage.c | 44 ++++++++++++++---------------
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 9308e96..a7ab482 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -169,32 +169,32 @@ void main(unsigned long bist)
 	u16 pm1_sts;
 
 	struct pei_data pei_data = {
-		pei_version: PEI_VERSION,
-		mchbar: DEFAULT_MCHBAR,
-		dmibar: DEFAULT_DMIBAR,
-		epbar: DEFAULT_EPBAR,
-		pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
-		smbusbar: SMBUS_IO_BASE,
-		wdbbar: 0x4000000,
-		wdbsize: 0x1000,
-		hpet_address: CONFIG_HPET_ADDRESS,
-		rcba: DEFAULT_RCBABASE,
-		pmbase: DEFAULT_PMBASE,
-		gpiobase: DEFAULT_GPIOBASE,
-		thermalbase: 0xfed08000,
-		system_type: 0, // 0 Mobile, 1 Desktop/Server
-		tseg_size: CONFIG_SMM_TSEG_SIZE,
-		spd_addresses: { 0xa0, 0x00, 0xa4, 0x00 },
-		ts_addresses: { 0x00, 0x00, 0x00, 0x00 },
-		ec_present: 0,
+		.pei_version = PEI_VERSION,
+		.mchbar = DEFAULT_MCHBAR,
+		.dmibar = DEFAULT_DMIBAR,
+		.epbar = DEFAULT_EPBAR,
+		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+		.smbusbar = SMBUS_IO_BASE,
+		.wdbbar = 0x4000000,
+		.wdbsize = 0x1000,
+		.hpet_address = CONFIG_HPET_ADDRESS,
+		.rcba = DEFAULT_RCBABASE,
+		.pmbase = DEFAULT_PMBASE,
+		.gpiobase = DEFAULT_GPIOBASE,
+		.thermalbase = 0xfed08000,
+		.system_type = 0, // 0 Mobile, 1 Desktop/Server
+		.tseg_size = CONFIG_SMM_TSEG_SIZE,
+		.spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
+		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
+		.ec_present = 0,
 		// 0 = leave channel enabled
 		// 1 = disable dimm 0 on channel
 		// 2 = disable dimm 1 on channel
 		// 3 = disable dimm 0+1 on channel
-		dimm_channel0_disabled: 2,
-		dimm_channel1_disabled: 2,
-		max_ddr3_freq: 1600,
-		usb_port_config: {
+		.dimm_channel0_disabled = 2,
+		.dimm_channel1_disabled = 2,
+		.max_ddr3_freq = 1600,
+		.usb_port_config = {
 			{ 1, 0, 0x0040 }, /* P0: Front port  (OC0) */
 			{ 1, 1, 0x0040 }, /* P1: Back port   (OC1) */
 			{ 1, 0, 0x0040 }, /* P2: MINIPCIE1   (no OC) */



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