[coreboot-gerrit] Patch set updated for coreboot: 85f3a8f Add new board: 945g-m4 (LGA775 i945GC i82801gx w83627ehg)

HAOUAS Elyes (ehaouas@noos.fr) gerrit at coreboot.org
Thu May 29 13:04:47 CEST 2014


HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5881

-gerrit

commit 85f3a8f6528872b17de8c5951bebd1969948e357
Author: Elyes <ehaouas at noos.fr>
Date:   Thu May 29 12:04:25 2014 +0200

    Add new board: 945g-m4 (LGA775 i945GC i82801gx w83627ehg)
    
    The console is running
    To fix: RAM init ... and more ...
    
    Change-Id: I7b00251e332ac005918cf7c3ed4bef8878bd145b
    Signed-off-by: Elyes <ehaouas at noos.fr>
---
 src/mainboard/nec/945g-m4/Kconfig                |  43 +++
 src/mainboard/nec/945g-m4/Makefile.inc           |  20 ++
 src/mainboard/nec/945g-m4/acpi/ec.asl            |  49 ++++
 src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl |  86 ++++++
 src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl | 103 +++++++
 src/mainboard/nec/945g-m4/acpi/platform.asl      |  91 +++++++
 src/mainboard/nec/945g-m4/acpi/superio.asl       |  92 +++++++
 src/mainboard/nec/945g-m4/acpi/thermal.asl       |  94 +++++++
 src/mainboard/nec/945g-m4/acpi/video.asl         |  43 +++
 src/mainboard/nec/945g-m4/acpi_tables.c          | 230 ++++++++++++++++
 src/mainboard/nec/945g-m4/board_info.txt         |   3 +
 src/mainboard/nec/945g-m4/cmos.layout            | 194 ++++++++++++++
 src/mainboard/nec/945g-m4/devicetree.cb          | 149 +++++++++++
 src/mainboard/nec/945g-m4/dsdt.asl               |  43 +++
 src/mainboard/nec/945g-m4/fadt.c                 | 155 +++++++++++
 src/mainboard/nec/945g-m4/irq_tables.c           |  61 +++++
 src/mainboard/nec/945g-m4/mainboard.c            |  65 +++++
 src/mainboard/nec/945g-m4/mptable.c              |  89 +++++++
 src/mainboard/nec/945g-m4/romstage.c             | 324 +++++++++++++++++++++++
 src/mainboard/nec/945g-m4/smihandler.c           |  49 ++++
 src/mainboard/nec/945g-m4/superio_hwm.c          | 161 +++++++++++
 src/mainboard/nec/945g-m4/superio_hwm.h          |  25 ++
 src/mainboard/nec/Kconfig                        |   4 +
 23 files changed, 2173 insertions(+)

diff --git a/src/mainboard/nec/945g-m4/Kconfig b/src/mainboard/nec/945g-m4/Kconfig
new file mode 100644
index 0000000..62ceca8
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/Kconfig
@@ -0,0 +1,43 @@
+if BOARD_NEC_945G_M4
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_LGA775
+	select NORTHBRIDGE_INTEL_I945
+#	select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
+	select CHECK_SLFRCS_ON_RESUME
+	select SOUTHBRIDGE_INTEL_I82801GX
+	select SUPERIO_WINBOND_W83627EHG
+	select EARLY_CBMEM_INIT
+	select HAVE_ACPI_TABLES
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
+	select HAVE_OPTION_TABLE
+	select HAVE_ACPI_RESUME
+	select BOARD_ROMSIZE_KB_512
+	select CHANNEL_XOR_RANDOMIZATION
+config MAINBOARD_DIR
+	string
+	default nec/945g-m4
+#config DCACHE_RAM_BASE
+#	hex
+#	default 0xfeffc000
+#config DCACHE_RAM_SIZE
+#	hex
+#	default 0x9900
+config MAINBOARD_PART_NUMBER
+	string
+	default "945G-M4"
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xf0000000
+config IRQ_SLOT_COUNT
+	int
+	default 18
+config MAX_CPUS
+	int
+	default 4
+#config VGA_BIOS_FILE
+#	string
+#	default "amipci_01.20"
+endif # BOARD_NEC_945G_M4
diff --git a/src/mainboard/nec/945g-m4/Makefile.inc b/src/mainboard/nec/945g-m4/Makefile.inc
new file mode 100644
index 0000000..30dfea9
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+romstage-y += ../../../northbridge/intel/i945/raminit.c
+ramstage-y += superio_hwm.c
diff --git a/src/mainboard/nec/945g-m4/acpi/ec.asl b/src/mainboard/nec/945g-m4/acpi/ec.asl
new file mode 100644
index 0000000..e6c30a0
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/ec.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Device(EC0)
+{
+	Name (_HID, EISAID("PNP0C09"))
+	Name (_UID, 1)
+
+	Method (_CRS, 0)
+	{
+		Name (ECMD, ResourceTemplate()
+		{
+			IO (Decode16, 0x62, 0x62, 0, 1)
+			IO (Decode16, 0x66, 0x66, 0, 1)
+		})
+
+		Return (ECMD)
+	}
+
+	Method (_REG, 2)
+	{
+		// This method is needed by Windows XP/2000
+		// for EC initialization before a driver
+		// is loaded
+	}
+
+	Name (_GPE, 23)	// GPI07 / GPE23 -> Runtime SCI
+
+	// TODO EC Query methods
+
+	// TODO Scope _SB devices for AC power, LID, Power button
+
+}
diff --git a/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl
new file mode 100644
index 0000000..bd3379b
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * i945
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// PCIe Graphics		0:1.0
+			Package() { 0x0001ffff, 0, 0, 16 },
+			Package() { 0x0001ffff, 1, 0, 17 },
+			Package() { 0x0001ffff, 2, 0, 18 },
+			Package() { 0x0001ffff, 3, 0, 19 },
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			//Package() { 0x001bffff, 0, 0, 16 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 16 },
+			Package() { 0x001cffff, 1, 0, 17 },
+			Package() { 0x001cffff, 2, 0, 18 },
+			Package() { 0x001cffff, 3, 0, 19 },
+			// USB and EHCI			0:1d.x
+			Package() { 0x001dffff, 0, 0, 23 },
+			Package() { 0x001dffff, 1, 0, 19 },
+			Package() { 0x001dffff, 2, 0, 18 },
+			Package() { 0x001dffff, 3, 0, 16 },
+			// AC97/IDE				0:1e.2, 0:1e.3
+			Package() { 0x001effff, 0, 0, 17 },
+			Package() { 0x001effff, 1, 0, 20 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, 0, 18 },
+			Package() { 0x001fffff, 1, 0, 19},
+		})
+	} Else {
+		Return (Package() {
+			// PCIe Graphics		0:1.0
+			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			//Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			// USB and EHCI			0:1d.x
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+			// AC97/IDE			0:1e.2, 0:1e.3
+			Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+		})
+	}
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000..c108d3f
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+	Return (Package() {
+		Package() { 0x0000ffff, 0, 0, 16},
+
+		Package() { 0x0001ffff, 0, 0, 20},
+		Package() { 0x0001ffff, 1, 0, 21},
+		Package() { 0x0001ffff, 2, 0, 22},
+		Package() { 0x0001ffff, 3, 0, 23},
+
+		Package() { 0x0002ffff, 0, 0, 21},
+		Package() { 0x0002ffff, 1, 0, 22},
+		Package() { 0x0002ffff, 2, 0, 23},
+		Package() { 0x0002ffff, 3, 0, 20},
+
+		Package() { 0x0003ffff, 0, 0, 22},
+		Package() { 0x0003ffff, 1, 0, 23},
+		Package() { 0x0003ffff, 2, 0, 20},
+		Package() { 0x0003ffff, 3, 0, 21},
+
+		Package() { 0x0004ffff, 0, 0, 23},
+		Package() { 0x0004ffff, 1, 0, 20},
+		Package() { 0x0004ffff, 2, 0, 21},
+		Package() { 0x0004ffff, 3, 0, 22},
+
+		Package() { 0x0005ffff, 0, 0, 19},
+		Package() { 0x0005ffff, 1, 0, 18},
+		Package() { 0x0005ffff, 2, 0, 17},
+		Package() { 0x0005ffff, 3, 0, 16},
+
+		Package() { 0x0006ffff, 0, 0, 18},
+		Package() { 0x0006ffff, 1, 0, 17},
+		Package() { 0x0006ffff, 2, 0, 16},
+		Package() { 0x0006ffff, 3, 0, 19},
+
+		Package() { 0x0009ffff, 0, 0, 21},
+		Package() { 0x0009ffff, 1, 0, 22},
+		Package() { 0x0009ffff, 2, 0, 23},
+		Package() { 0x0009ffff, 3, 0, 20},
+	})
+} Else {
+	Return (Package() {
+		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+
+		Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
+
+		Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+
+		Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKF, 0},
+
+		Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKG, 0},
+
+		Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},
+		Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+		Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0006ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
+		Package() { 0x0006ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+
+		Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0009ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0009ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0009ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+	})
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi/platform.asl b/src/mainboard/nec/945g-m4/acpi/platform.asl
new file mode 100644
index 0000000..2e4223c
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/platform.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+	// Call a trap so SMI can prepare for Sleep as well.
+	// TRAP(0x55)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	// CPU specific part
+
+	// Notify PCI Express slots in case a card
+	// was inserted while a sleep state was active.
+
+	// Are we going to S3?
+	If (LEqual(Arg0, 3)) {
+		// ..
+	}
+
+	// Are we going to S4?
+	If (LEqual(Arg0, 4)) {
+		// ..
+	}
+
+	// TODO: Windows XP SP2 P-State restore
+
+	Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi/superio.asl b/src/mainboard/nec/945g-m4/acpi/superio.asl
new file mode 100644
index 0000000..997a33a
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/superio.asl
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+Device (SIO1)
+{
+	Name (_HID, EISAID("PNP0A05"))
+	Name (_UID, 1)
+
+	Device (UAR1)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 1)
+		Name(_DDN, "COM1")
+
+		Method (_STA, 0)
+		{
+			// always enable for now
+			Return (0x0f)
+		}
+
+		Method (_DIS, 0) { /* NOOP */ }
+
+		Name (_PRS, ResourceTemplate() {
+			StartDependentFn(0, 1) {
+				IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
+				IRQNoFlags() { 4 }
+			} EndDependentFn()
+		})
+
+		Method (_CRS, 0)
+		{
+			Return(ResourceTemplate() {
+				IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
+				IRQNoFlags() { 4 }
+			})
+		}
+		// Some methods need an implementation here:
+		// missing: _STA, _DIS, _CRS, _PRS,
+		// missing: _SRS, _PS0, _PS3
+	}
+
+	Device (UAR2)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 2)
+		Name(_DDN, "COM2")
+
+		Method (_STA, 0)
+		{
+			// always enable for now
+			Return (0x0f)
+		}
+
+		Method (_DIS, 0) { /* NOOP */ }
+
+		Name (_PRS, ResourceTemplate() {
+			StartDependentFn(0, 1) {
+				IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
+				IRQNoFlags() { 3 }
+			} EndDependentFn()
+		})
+
+		Method (_CRS, 0)
+		{
+			Return(ResourceTemplate() {
+				IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
+				IRQNoFlags() { 3 }
+			})
+		}
+		// Some methods need an implementation here:
+		// missing: _STA, _DIS, _CRS, _PRS,
+		// missing: _SRS, _PS0, _PS3
+	}
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi/thermal.asl b/src/mainboard/nec/945g-m4/acpi/thermal.asl
new file mode 100644
index 0000000..d1774d4
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/thermal.asl
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+
+		// FIXME these could/should be read from the
+		// GNVS area, so they can be controlled by
+		// coreboot
+		Name(TC1V, 0x04)
+		Name(TC2V, 0x03)
+		Name(TSPV, 0x64)
+
+		// At which temperature should the OS start
+		// active cooling?
+		Method (_AC0, 0, Serialized)
+		{
+			Return (0xf5c) // Value for Rocky
+		}
+
+		// Method (_AC1, 0, Serialized)
+		// {
+		// 	Return (0xf5c)
+		// }
+
+		// Critical shutdown temperature
+		Method (_CRT, 0, Serialized)
+		{
+			Return (Add (0x0aac, 0x50)) // FIXME
+		}
+
+		// CPU throttling start temperature
+		Method (_PSV, 0, Serialized)
+		{
+			Return (0xaaf) // FIXME
+		}
+
+		// Get DTS Temperature
+		Method (_TMP, 0, Serialized)
+		{
+			Return (0xaac) // FIXME
+		}
+
+		// Processors used for active cooling
+		Method (_PSL, 0, Serialized)
+		{
+			If (MPEN) {
+				Return (Package() {\_PR.CPU1, \_PR.CPU2})
+			}
+			Return (Package() {\_PR.CPU1})
+		}
+
+		// TC1 value for passive cooling
+		Method (_TC1, 0, Serialized)
+		{
+			Return (TC1V)
+		}
+
+		// TC2 value for passive cooling
+		Method (_TC2, 0, Serialized)
+		{
+			Return (TC2V)
+		}
+
+		// Sampling period for passive cooling
+		Method (_TSP, 0, Serialized)
+		{
+			Return (TSPV)
+		}
+
+
+	}
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi/video.asl b/src/mainboard/nec/945g-m4/acpi/video.asl
new file mode 100644
index 0000000..3ececa9
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/video.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+	// TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+	// TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi_tables.c b/src/mainboard/nec/945g-m4/acpi_tables.c
new file mode 100644
index 0000000..e6a517e
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi_tables.c
@@ -0,0 +1,230 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include "southbridge/intel/i82801gx/nvs.h"
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	memset((void *)gnvs, 0, sizeof(*gnvs));
+	gnvs->apic = 1;
+	gnvs->mpen = 1; /* Enable Multi Processing */
+
+	/* Enable both COM ports */
+	gnvs->cmap = 0x01;
+	gnvs->cmbp = 0x01;
+
+	/* IGD Displays */
+	gnvs->ndid = 3;
+	gnvs->did[0] = 0x80000100;
+	gnvs->did[1] = 0x80000240;
+	gnvs->did[2] = 0x80000410;
+	gnvs->did[3] = 0x80000410;
+	gnvs->did[4] = 0x00000005;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	/* INT_SRC_OVR */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	generate_cpu_entries();
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
+
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	int i;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_xsdt_t *xsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_mcfg_t *mcfg;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+	acpi_header_t *slic;
+#endif
+	acpi_header_t *ssdt;
+	acpi_header_t *dsdt;
+
+	current = start;
+
+	/* Align ACPI tables to 16byte */
+	ALIGN_CURRENT;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	ALIGN_CURRENT;
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+	ALIGN_CURRENT;
+	xsdt = (acpi_xsdt_t *) current;
+	current += sizeof(acpi_xsdt_t);
+	ALIGN_CURRENT;
+
+	/* clear all table memory */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, xsdt);
+	acpi_write_rsdt(rsdt);
+	acpi_write_xsdt(xsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
+
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	ALIGN_CURRENT;
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
+
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, madt);
+
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, mcfg);
+
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	ALIGN_CURRENT;
+	acpi_create_facs(facs);
+
+	dsdt = (acpi_header_t *) current;
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+
+	ALIGN_CURRENT;
+
+	/* Pack GNVS into the ACPI table area */
+	for (i=0; i < dsdt->length; i++) {
+		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+			break;
+		}
+	}
+
+	/* And fill it */
+	acpi_create_gnvs((global_nvs_t *)current);
+
+	current += 0x100;
+	ALIGN_CURRENT;
+
+	/* And tell SMI about it */
+	smm_setup_structures((void *)current, NULL, NULL);
+
+	/* We patched up the DSDT, so we need to recalculate the checksum */
+	dsdt->checksum = 0;
+	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
+		     dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
+	slic = (acpi_header_t *)current;
+	current += acpi_create_slic(current);
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, slic);
+#endif
+
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+	ALIGN_CURRENT;
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "current = %lx\n", current);
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
diff --git a/src/mainboard/nec/945g-m4/board_info.txt b/src/mainboard/nec/945g-m4/board_info.txt
new file mode 100644
index 0000000..ed23062
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/board_info.txt
@@ -0,0 +1,3 @@
+Category: µATX 24.4 cm x 24.4 cm Form Factor
+Board URL: http://www.nec-computers.com/support2/pib.asp?platform=spec_veracruz&mode=default&source=1409
+Flashrom support: y
diff --git a/src/mainboard/nec/945g-m4/cmos.layout b/src/mainboard/nec/945g-m4/cmos.layout
new file mode 100644
index 0000000..b3e8c4e
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/cmos.layout
@@ -0,0 +1,194 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+416        512       s       0        boot_devices
+#928         40       r       0        unused
+
+# coreboot config options: mainboard specific options
+948          2       e       8        cpufan_cruise_control
+950          2       e       8        sysfan_cruise_control
+952          4       e       9        cpufan_speed
+#956          4       e       10       cpufan_temperature
+960          4       e       9        sysfan_speed
+#964          4       e       10       sysfan_temperature
+
+968          1       e       2        ethernet1
+969          1       e       2        ethernet2
+970          1       e       2        ethernet3
+
+#971          13       r       0        unused
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# ram initialization internal data
+1024         8       r       0        C0WL0REOST
+1032         8       r       0        C1WL0REOST
+1040         8       r       0        RCVENMT
+1048         4       r       0        C0DRT1
+1052         4       r       0        C1DRT1
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+# Fan Cruise Control
+8     0     Disabled
+8     1     Speed
+#8     2     Thermal
+# Fan Speed (Rotations per Minute)
+9     0     5625
+9     1     5192
+9     2     4753
+9     3     4326
+9     4     3924
+9     5     3552
+9     6     3214
+9     7     2909
+9     8     2636
+9     9     2393
+9    10     2177
+9    11     1985
+9    12     1814
+9    13     1662
+9    14     1527
+9    15     1406
+#
+# Temperature (°C/°F)
+#10     0     30/86
+#10     1     33/91
+#10     2     36/96
+#10     3     39/102
+#10     4     42/107
+#10     5     45/113
+#10     6     48/118
+#10     7     51/123
+#10     8     54/129
+#10     9     57/134
+#10    10     60/140
+#10    11     63/145
+#10    12     66/150
+#10    13     69/156
+#10    14     72/161
+#10    15     75/167
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/nec/945g-m4/devicetree.cb b/src/mainboard/nec/945g-m4/devicetree.cb
new file mode 100644
index 0000000..2f4020e
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/devicetree.cb
@@ -0,0 +1,149 @@
+#lspci
+#-[0000:00]-+-00.0 Intel Corporation 82945G/GZ/P/PL Memory Controller Hub [8086:2770]
+#           +-01.0-[01]--+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] RV370 [Radeon X300] [1002:5b60] <- PCIe card. integrated vga is an intel, desabled by vendor bios.
+#           | \-00.1 Advanced Micro Devices, Inc. [AMD/ATI] RV370 [Radeon X300 SE] [1002:5b70]
+#           +-1c.0-[02]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168]
+#           +-1d.0 Intel Corporation NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8]
+#           +-1d.1 Intel Corporation NM10/ICH7 Family USB UHCI Controller #2 [8086:27c9]
+#           +-1d.2 Intel Corporation NM10/ICH7 Family USB UHCI Controller #3 [8086:27ca]
+#           +-1d.3 Intel Corporation NM10/ICH7 Family USB UHCI Controller #4 [8086:27cb]
+#           +-1d.7 Intel Corporation NM10/ICH7 Family USB2 EHCI Controller [8086:27cc]
+#           +-1e.0-[03]----02.0 Philips Semiconductors SAA7146 [1131:7146]
+#           +-1e.2 Intel Corporation 82801G (ICH7 Family) AC'97 Audio Controller [8086:27de]
+#           +-1f.0 Intel Corporation 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8]
+#           +-1f.1 Intel Corporation 82801G (ICH7 Family) IDE Controller [8086:27df]
+#           +-1f.2 Intel Corporation NM10/ICH7 Family SATA Controller [IDE mode] [8086:27c0]
+#           \-1f.3 Intel Corporation NM10/ICH7 Family SMBus Controller [8086:27da]
+#end lspci
+chip northbridge/intel/i945
+	device cpu_cluster 0 on
+		chip cpu/intel/socket_LGA775
+			device lapic 0 on end
+		end
+	end
+	device domain 0 on
+		device pci 00.0 on end # host bridge +-00.0  Intel Corporation 82945G/GZ/P/PL Memory Controller Hub [8086:2770]
+		device pci 01.0 on end # i945 PCIe root port
+					#+-01.0-[01]--+-00.0  Advanced Micro Devices, Inc. [AMD/ATI] RV370 [Radeon X300] [1002:5b60]
+                      			#     \-00.1  Advanced Micro Devices, Inc. [AMD/ATI] RV370 [Radeon X300 SE] [1002:5b70]
+          	#device pci 02.0 on end # vga controller +-02.0  Intel Corporation 82945G/GZ Integrated Graphics Controller [8086:2772]
+                chip southbridge/intel/i82801gx
+			register "pirqa_routing" = "0x8a" # OS will change it:"0x0a" found via dmesg (linux on vendor bios)
+			register "pirqb_routing" = "0x85" # OS will change it:"0x05" found via dmesg
+			register "pirqc_routing" = "0x8b" # OS will change it:"0x0b"found via dmesg
+			register "pirqd_routing" = "0x8b" # OS will change it:"0x0b" found via dmesg
+			register "pirqe_routing" = "0x80" # ?? via dmesg: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled
+			register "pirqf_routing" = "0x80" # ?? via dmesg: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled
+			register "pirqg_routing" = "0x80" # ?? via dmesg: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled
+			register "pirqh_routing" = "0x8a" # OS will change it: "0x0a"found via dmsg
+			# GPI routing
+			#  0 No effect (default)
+			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+			#  2 SCI (if corresponding GPIO_EN bit is also set)
+			register "gpi13_routing" = "1"
+                        register "ide_legacy_combined" = "0x0"
+                        register "ide_enable_primary" = "0x1"
+                        register "ide_enable_secondary" = "0x0"
+                        register "sata_ahci" = "0x1"
+			device pci 1c.0 on end #  Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168]
+	           	device pci 1d.0 on end #Intel Corporation NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8]
+	           	device pci 1d.1 on end # Intel Corporation NM10/ICH7 Family USB UHCI Controller #2 [8086:27c9]
+	           	device pci 1d.2 on end #Intel Corporation NM10/ICH7 Family USB UHCI Controller #3 [8086:27ca]
+	           	device pci 1d.3 on end #Intel Corporation NM10/ICH7 Family USB UHCI Controller #4 [8086:27cb]
+	           	device pci 1d.7 on end #Intel Corporation NM10/ICH7 Family USB2 EHCI Controller [8086:27cc]
+	           	device pci 1e.0 on end #-[02]----02.0  Philips Semiconductors SAA7146 [1131:7146]
+			device pci 1e.2 on end # Intel Corporation 82801G (ICH7 Family) AC'97 Audio Controller [8086:27de]
+			device pci 1f.0 on  # Intel Corporation 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8]
+
+				chip superio/winbond/w83627ehg	# Super I/O
+					#Found Winbond W83627EHF/EF/EHG/EG (id=0x88, rev=0x63) at 0x2e
+					#Register dump:
+					#idx 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+					#val 88 63 ff 00 44 00 00 ff 50 05 00 00 83 20 00 ff
+					#def 88 MM ff 00 MM 00 MM RR 50 04 00 RR 00 21 00 00
+			              device pnp 2e.0 on		#LDN 0x00 (Floppy)
+					io 0x60 = 0x3f0			#idx 30 60 61 70 74 f0 f1 f2 f4 f5
+					irq 0x70 = 6			#val 01 03 f0 06 02 8e 00 ff 00 00
+					drq 0x74 = 2			#def 01 03 f0 06 02 8e 00 ff 00 00
+				      end
+
+				      device pnp 2e.1 on		#LDN 0x01 (Parallel port)
+					io 0x60 = 0x378			#idx 30 60 61 70 74 f0
+					irq 0x70 = 7			#val 01 03 78 07 04 3c
+					drq 0x74 = 3			#def 01 03 78 07 04 3f
+				      end
+			              device pnp 2e.2 on		#LDN 0x02 (COM1)
+					io 0x60 = 0x3f8			#idx 30 60 61 70 f0
+					irq 0x70 = 4			#val 01 03 f8 04 00
+									#def 01 03 f8 04 00
+			              end
+
+
+			              device pnp 2e.3 off		#LDN 0x03 (COM2)
+					io 0x60 = 0x2f8			#idx 30 60 61 70 f0 f1
+					irq 0x70 = 3			#val 01 02 f8 03 00 04
+									#def 01 02 f8 03 00 00
+			              end
+
+				      device pnp 2e.5 on		#LDN 0x05 (Keyboard)
+									#idx 30 60 61 62 63 70 72 f0
+									#val 01 00 60 00 64 01 0c 82
+									#def 01 00 60 00 64 01 0c 83
+			              end
+			              device pnp 2e.106 on		#LDN 0x06 (Serial flash interface)
+					io 0x60 = 0x100			#idx 30 62 63
+									#val 00 ff ff
+									#def 00 00 00
+			              end
+					#----
+					#LDN 0x07 (GPIO 1, GPIO 6, game port, MIDI port)
+					#idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 f7
+					#val 01 00 00 00 00 00 5f 5f 00 00 ff ff ff 00
+					#def 00 02 01 03 30 09 ff 00 00 00 ff 00 00 00
+			              device pnp 2e.007 on		# GPIO 1
+			              end
+			              device pnp 2e.107 off		# Game port
+			                io 0x60 = 0x201
+			              end
+			              device pnp 2e.207 on		# MIDI
+			                io 0x62 = 0x330
+			                irq 0x70 = 0xa
+			              end
+			              device pnp 2e.307 on		# GPIO 6
+			              end
+			              device pnp 2e.8 off		#LDN 0x08 (WDTO#, PLED)
+									#idx 30 f5 f6 f7
+									#val 00 ff 00 ff
+									#def 00 00 00 00
+			              end
+					#----
+					#LDN 0x09 (GPIO 2, GPIO 3, GPIO 4, GPIO 5, SUSLED)
+					#idx 30 e0 e1 e2 e3 e4 e5 f0 f1 f2 f3 f4 f5 f6 f7
+					#val 0e df 00 20 ff ff ff 8c 8c 00 40 df 00 00 20
+					#def 00 ff 00 00 ff 00 00 ff 00 00 00 ff 00 00 00
+			              device pnp 2e.009 on		# GPIO 2
+			              end
+			              device pnp 2e.109 on		# GPIO 3
+			              end
+			              device pnp 2e.209 on		# GPIO 4
+			              end
+			              device pnp 2e.309 on		# GPIO 5
+			              end
+			              device pnp 2e.a on		#LDN 0x0a (ACPI)
+									#idx 30 70 e0 e1 e2 e3 e4 e5 e6 e7 e8 f2 f3 f4 f6 f7
+									#val 01 00 01 00 ff 04 00 00 1c 10 09 7c 00 00 00 00
+									#def 00 00 01 00 ff 08 00 RR 00 00 RR 7c 00 00 00 00
+			              end
+			              device pnp 2e.b on		#LDN 0x0b (Hardware monitor)
+					io 0x60 = 0x290			#idx 30 60 61 70 f0 f1
+					irq 0x70 = 0			#val 01 0a 10 00 c1 00
+									#def 00 00 00 00 c1 00
+			              end
+			         end
+			   end
+			device pci 1f.1 on end # Intel Corporation 82801G (ICH7 Family) IDE Controller [8086:27df]
+			device pci 1f.2 on end # Intel Corporation NM10/ICH7 Family SATA Controller [IDE mode] [8086:27c0]
+			device pci 1f.3 on end # Intel Corporation NM10/ICH7 Family SMBus Controller [8086:27da]
+                      end
+                end
+end
\ No newline at end of file
diff --git a/src/mainboard/nec/945g-m4/dsdt.asl b/src/mainboard/nec/945g-m4/dsdt.asl
new file mode 100644
index 0000000..f30c12d
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/dsdt.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock ("dsdt.aml", "DSDT", 1, "COREv4", "COREBOOT", 0x00000108)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+
+	// General Purpose Events
+	//#include "acpi/gpe.asl"
+
+	//#include "acpi/thermal.asl"
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <northbridge/intel/i945/acpi/i945.asl>
+			#include <southbridge/intel/i82801gx/acpi/ich7.asl>
+		}
+	}
+
+	/* Chipset specific sleep states */
+	#include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/nec/945g-m4/fadt.c b/src/mainboard/nec/945g-m4/fadt.c
new file mode 100644
index 0000000..b55f628
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/fadt.c
@@ -0,0 +1,155 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+#include <cpu/x86/smm.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 1;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->model = 1;
+	fadt->preferred_pm_profile = PM_MOBILE;
+
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
+
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x20;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x28;
+	fadt->gpe1_blk = 0;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	// XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0)
+	fadt->pm2_cnt_len = 2;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
+	fadt->p_lvl2_lat = 1;
+	fadt->p_lvl3_lat = 85;
+	fadt->flush_size = 1024;
+	fadt->flush_stride = 16;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 0;
+	fadt->day_alrm = 0xd;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = 0x03;
+
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 0;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/nec/945g-m4/irq_tables.c b/src/mainboard/nec/945g-m4/irq_tables.c
new file mode 100644
index 0000000..5e2566b
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/irq_tables.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 200x TODO <TODO at TODO>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,		/* u32 signature */
+	PIRQ_VERSION,		/* u16 version */
+	32 + 16 * 14,		/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x1f << 3) | 0x0,	/* Interrupt router dev */
+	0,			/* IRQs devoted exclusively to PCI usage */
+	0x8086,			/* Vendor */
+	0x27b0,			/* Device */
+	0,			/* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0xb,			/* Checksum (has to be set to some value that
+				 * would give 0 after the sum of all bytes
+				 * for this structure (including checksum).
+                                 */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
+		{0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x1e << 3) | 0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x1f << 3) | 0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x1d << 3) | 0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x60, 0xdcf8}}, 0x0, 0x0},
+		{0x00, (0x1b << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x1c << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
+		{0x02, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x20, 0x0},
+		{0x03, (0x03 << 3) | 0x0, {{0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x4, 0x0},
+		{0x03, (0x04 << 3) | 0x0, {{0x62, 0xdcf8}, {0x6b, 0xdcf8}, {0x60, 0xdcf8}, {0x68, 0xdcf8}}, 0x5, 0x0},
+		{0x03, (0x05 << 3) | 0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x6, 0x0},
+		{0x03, (0x01 << 3) | 0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}}, 0x1, 0x0},
+		{0x03, (0x02 << 3) | 0x0, {{0x63, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x2, 0x0},
+		{0x03, (0x08 << 3) | 0x0, {{0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/nec/945g-m4/mainboard.c b/src/mainboard/nec/945g-m4/mainboard.c
new file mode 100644
index 0000000..568a5c3
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/mainboard.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <device/device.h>
+#include <console/console.h>
+#if CONFIG_VGA_ROM_RUN
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include "superio_hwm.h"
+
+#if CONFIG_VGA_ROM_RUN
+static int int15_handler(void)
+{
+#define BOOT_DISPLAY_DEFAULT	0
+#define BOOT_DISPLAY_CRT	(1 << 0)
+#define BOOT_DISPLAY_TV		(1 << 1)
+#define BOOT_DISPLAY_EFP	(1 << 2)
+#define BOOT_DISPLAY_LCD	(1 << 3)
+#define BOOT_DISPLAY_CRT2	(1 << 4)
+#define BOOT_DISPLAY_TV2	(1 << 5)
+#define BOOT_DISPLAY_EFP2	(1 << 6)
+#define BOOT_DISPLAY_LCD2	(1 << 7)
+
+	printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+			  __func__, X86_AX, X86_BX, X86_CX, X86_DX);
+
+	switch (X86_AX) {
+	case 0x5f35: /* Boot Display */
+		X86_AX = 0x005f; // Success
+		X86_CL = BOOT_DISPLAY_DEFAULT;
+		break;
+	case 0x5f40: /* Boot Panel Type */
+		// M.x86.R_AX = 0x015f; // Supported but failed
+		X86_AX = 0x005f; // Success
+		X86_CL = 3; // Display ID
+		break;
+	default:
+		/* Interrupt was not handled */
+		return 0;
+	}
+
+	/* Interrupt handled */
+	return 1;
+}
+#endif
diff --git a/src/mainboard/nec/945g-m4/mptable.c b/src/mainboard/nec/945g-m4/mptable.c
new file mode 100644
index 0000000..95a34da
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/mptable.c
@@ -0,0 +1,89 @@
+/* generated by MPTable, version 2.0.15*/
+/* as modified by RGM for coreboot */
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#define INTA 0x00
+#define INTB 0x01
+#define INTC 0x02
+#define INTD 0x03
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+{
+	mc->mpc_length += length;
+	mc->mpc_entry_count++;
+}
+static void my_smp_write_bus(struct mp_config_table *mc,
+			     unsigned char id, const char *bustype)
+{
+	struct mpc_config_bus *mpc;
+	mpc = smp_next_mpc_entry(mc);
+	memset(mpc, '\0', sizeof(*mpc));
+	mpc->mpc_type = MP_BUS;
+	mpc->mpc_busid = id;
+	memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+	smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+static void *smp_write_config_table(void *v)
+{
+        struct mp_config_table *mc;
+        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+        mptable_init(mc, LOCAL_APIC_ADDR);
+        smp_write_processors(mc);
+	/* Bus: Bus ID  Type */
+	my_smp_write_bus(mc, 0, "PCI   ");
+	my_smp_write_bus(mc, 1, "PCI   ");
+	my_smp_write_bus(mc, 2, "PCI   ");
+	my_smp_write_bus(mc, 3, "PCI   ");
+	my_smp_write_bus(mc, 4, "ISA   ");
+	/* I/O APICs: APIC ID  Version  State  Address */
+	smp_write_ioapic(mc, 0x1, 0x20, 0xfec00000);
+	/* I/O Ints: Type  Polarity  Trigger  Bus ID  IRQ  APIC ID  PIN#*/
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x0, 0x1, 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x1, 0x1, 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x0, 0x1, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x3, 0x1, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x4, 0x1, 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x6, 0x1, 0x6);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x7, 0x1, 0x7);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x8, 0x1, 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x9, 0x1, 0x9);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xc, 0x1, 0xc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xd, 0x1, 0xd);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xe, 0x1, 0xe);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xf, 0x1, 0xf);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x01 << 2) | INTA, 0x1, 0x10);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (0x00 << 2) | INTA, 0x1, 0x10);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1e << 2) | INTA, 0x1, 0x11);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTA, 0x1, 0x12);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTB, 0x1, 0x13);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTA, 0x1, 0x17);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTB, 0x1, 0x13);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTC, 0x1, 0x12);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTD, 0x1, 0x10);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1c << 2) | INTA, 0x1, 0x10);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | INTA, 0x1, 0x10);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x02 << 2) | INTA, 0x1, 0x13);
+	/* Local Ints: Type  Polarity  Trigger  Bus ID  IRQ  APIC ID  PIN# */
+	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1);
+/* mptable_lintsrc(mc, isa_bus); */
+	/* Compute the checksums */
+	return mptable_finalize(mc);
+}
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr, 1);
+	return (unsigned long)smp_write_config_table(v);
+}
+/*MP Config Extended Table Entries:
+--
+System Address Space
+ bus ID: 0 address type: I/O address
+ address base: 0x600000000000
+ address range: 0x148000000000
+Extended Table HOSED!
+*/
\ No newline at end of file
diff --git a/src/mainboard/nec/945g-m4/romstage.c b/src/mainboard/nec/945g-m4/romstage.c
new file mode 100644
index 0000000..f64a179
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/romstage.c
@@ -0,0 +1,324 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <lib.h>
+#include <cbmem.h>
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627ehg/w83627ehg.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include <northbridge/intel/i945/i945.h>
+#include <northbridge/intel/i945/raminit.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
+#define LPC_DEV PCI_DEV(0, 0x1f, 0)
+void setup_ich7_gpios(void)
+{ /*
+./inteltool -g
+CPU: ID 0xf65, Processor Type 0x0, Family 0xf, Model 0x6, Stepping 0x5
+Northbridge: 8086:2770 (945P) <-- in fact, it is a i945GC
+Southbridge: 8086:27b8 (ICH7)
+============= GPIOS =============
+GPIOBASE = 0x0480 (IO)
+gpiobase+0x0000: 0x1f9fffc3 (GPIO_USE_SEL)
+gpiobase+0x0004: 0xe0e8ffc3 (GP_IO_SEL)
+gpiobase+0x0008: 0x00000000 (RESERVED)
+gpiobase+0x000c: 0xebffffbf (GP_LVL)
+gpiobase+0x0010: 0x00000000 (RESERVED)
+gpiobase+0x0014: 0x00000000 (RESERVED)
+gpiobase+0x0018: 0x00000000 (GPO_BLINK)
+gpiobase+0x001c: 0x00000000 (RESERVED)
+gpiobase+0x0020: 0x00000000 (RESERVED)
+gpiobase+0x0024: 0x00000000 (RESERVED)
+gpiobase+0x0028: 0x00000000 (RESERVED)
+gpiobase+0x002c: 0x0000af03 (GPI_INV)
+gpiobase+0x0030: 0x000000ff (GPIO_USE_SEL2)
+gpiobase+0x0034: 0x000000f0 (GP_IO_SEL2)
+gpiobase+0x0038: 0x000000f7 (GP_LVL2)
+gpiobase+0x003c: 0x00000000 (RESERVED)
+*/
+	printk(BIOS_DEBUG, " GPIOS...");
+	/* General Registers */
+	outl(0x1f9fffc3, DEFAULT_GPIOBASE + GPIO_USE_SEL);
+	outl(0xe0e8ffc3, DEFAULT_GPIOBASE + GP_IO_SEL);
+	outl(0xebffffbf, DEFAULT_GPIOBASE + GP_LVL);
+	/* Output Control Registers */
+	outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK);
+	/* Input Control Registers */
+	outl(0x0000af03, DEFAULT_GPIOBASE + GPI_INV);
+	outl(0x000000ff, DEFAULT_GPIOBASE + GPIO_USE_SEL2);
+	outl(0x000000f0, DEFAULT_GPIOBASE + GP_IO_SEL2);
+	outl(0x000000f7, DEFAULT_GPIOBASE + GP_LVL2);
+}
+static void ich7_enable_lpc(void)
+{
+// see http://macbook.donderklumpen.de/coreboot/ section Stage 2: ROM stage
+/* lspci -nnvvvxxx -s 00:1f.0
+lspci -nnvvvxxx -s 00:1f.0
+00:1f.0 ISA bridge [0601]: Intel Corporation 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8] (rev 01)
+	Subsystem: Packard Bell B.V. Device [1631:e015]
+	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+	Latency: 0
+	Capabilities: [e0] Vendor Specific Information: Len=0c <?>
+	Kernel driver in use: lpc_ich
+	Kernel modules: intel_rng
+00: 86 80 b8 27 07 00 10 02 01 00 01 06 00 00 80 00
+10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+20: 00 00 00 00 00 00 00 00 00 00 00 00 31 16 15 e0
+30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
+40: 01 08 00 00 80 00 00 00 81 04 00 00 10 00 00 00
+50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+60: 8a 85 8b 8b d0 00 00 00 80 80 80 8a 00 00 00 00
+70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80: 10 00 0f 34 01 0a fc 00 01 47 fc 00 00 00 00 00
+90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+a0: 28 06 00 00 39 00 00 00 13 00 00 00 00 03 00 00
+b0: 00 00 f0 00 00 00 00 00 00 00 02 80 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 33 22 11 00 67 45 00 00 c0 80 00 00 00 00 00 00
+e0: 09 00 0c 10 a8 00 24 00 00 00 00 00 00 00 00 00
+f0: 01 c0 d1 fe 00 00 00 00 86 0f 01 00 00 00 00 00*/
+	// Enable Serial IRQ
+	pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); /* datasheet page 363 default value 0x10 */
+	// LPC I/O decode range
+	pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); /* datasheet: default value 0x0000 */
+	// LPC Interface Enables
+	pci_write_config16(LPC_DEV, LPC_EN, 0x340f); /* datasheet: default value 0x0000 */
+// PIRQ [A-D] -> see devicetree.cb
+//	pci_write_config8(LPC_DEV, 0x60, 0x8a);
+//	pci_write_config8(LPC_DEV, 0x61, 0x85);
+//	pci_write_config8(LPC_DEV, 0x62, 0x8b);
+//	pci_write_config8(LPC_DEV, 0x63, 0x8b);
+// PIRQ [E-H]*/ > see devicetree.cb
+//	pci_write_config8(LPC_DEV, 0x68, 0x80);
+//	pci_write_config8(LPC_DEV, 0x69, 0x80);
+//	pci_write_config8(LPC_DEV, 0x6a, 0x80);
+//	pci_write_config8(LPC_DEV, 0x6b, 0x8a);
+/* GEN1_DEC. LPC interface generic decode Rang1 */
+	pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01);
+//	pci_write_config16(LPC_DEV, 0x84, 0x0a01); /* datasheet page 364: conf32 - default value 0x00000000 */
+//	pci_write_config16(LPC_DEV, 0x86, 0x00fc);
+	/* GEN2_DEC. LPC interface generic decode Rang2 */
+	pci_write_config32(LPC_DEV, 0x88, 0x00fc4701);
+//	pci_write_config16(LPC_DEV, 0x88, 0x4701); /* datasheet - conf32: default value 0x00000000 */
+//	pci_write_config16(LPC_DEV, 0x8a, 0x00fc);
+	/* GEN3_DEC. LPC interface generic decode Rang3 */
+//	pci_write_config32(LPC_DEV, 0x8c,0x00000000);
+//	pci_write_config16(LPC_DEV, 0x8c, 0x0000); /* datasheet - conf32: default value 0x00000000 */
+//	pci_write_config16(LPC_DEV, 0x8e, 0x0000);
+	/* GEN4_DEC. LPC interface generic decode Rang4 */
+//	pci_write_config32(LPC_DEV, 0x90, 0x00000000);
+//	pci_write_config32(LPC_DEV, 0x90, 0x00000000);
+}
+static void rcba_config(void)
+{
+	/* Set up virtual channel 0 */
+	/*./inteltool -r |grep -i 0x0014
+	 	 0x0014: 0x80000001 */
+//	RCBA32(V0CTL) = 0x80000001; see i945/ ich7_setup_dmi_rcrb()
+	/* ./inteltool -r |grep -i 0x001C
+	 	 0x001c: 0x03128010 */
+//	RCBA32(V1CAP) = 0x03128010; see i945/ ich7_setup_dmi_rcrb()
+	/* Device 1f interrupt pin register */
+	/*
+	./inteltool -r |grep -i 0x3100
+		 0x3100: 0x00042210 */
+	RCBA32(D31IP) = 0x00042210;
+	/* Device 1d interrupt pin register */
+	/* ./inteltool -r |grep -i 0x310c
+	         0x310c: 0x00214321 */
+	RCBA32(D28IP) = 0x00214321;
+	/* HD Audio Interrupt */
+	RCBA32(D27IP) = 0x00000001;
+	/* dev irq route register */
+	/*./inteltool -r |grep -i 0x3140
+	       0x3140: 0x32410132 */
+	RCBA16(D31IR) = 0x3241;
+	RCBA16(D30IR) = 0x0132;
+//
+	/* ./inteltool -r |grep -i 0x3144
+	       0x3144: 0x32100237*/
+	RCBA16(D29IR) = 0x3210;
+	RCBA16(D28IR) = 0x0237;
+	/*./inteltool -r |grep -i 0x3148
+	       0x3148: 0x00003210 */
+	RCBA16(D27IR) = 0x0000;
+//
+	/* Enable IOAPIC */
+	/*./inteltool -r |grep -i 0x31f
+	      0x31fc: 0x03000000 */
+	//RCBA8(0x31ff) = 0x00;
+	RCBA32(0x31fc) |= 3 << 24;
+	/* Enable upper 128bytes of CMOS */
+	RCBA32(RC) = (1 << 2);
+	/* Enable PCIe Root Port Clock Gate */
+	/* ./inteltool -r |grep -i 0x341c
+		0x341c: 0x00000001 */
+	RCBA32(CG) = 0x00000001;
+}
+static void early_ich7_init(void)
+{
+	uint8_t reg8;
+	uint32_t reg32;
+	// program secondary mlt XXX byte?
+	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+	// reset rtc power status
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+	reg8 &= ~(1 << 2);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+	// usb transient disconnect
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+	reg8 |= (3 << 0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+	reg32 |= (1 << 29) | (1 << 17);
+	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+	reg32 |= (1 << 31) | (1 << 27);
+	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+	/*./inteltool -r |grep -i 0x0088
+		0x0088: 0x0011d000 */
+	RCBA32(0x0088) = 0x0011d000;
+	/*./inteltool -r |grep -i 0x01fc
+		0x01fc: 0x0000060f */
+	RCBA16(0x01fc) = 0x060f;
+	/*./inteltool -r |grep -i 0x01f4
+		0x01f4: 0x86000040 */
+	RCBA32(0x01f4) = 0x86000040;
+	/* ./inteltool -r |grep -i 0x0214
+		0x0214: 0x10030509*/
+	RCBA32(0x0214) = 0x10030549;
+	/*./inteltool -r |grep -i 0x0218
+		0x0218: 0x00020504 */
+	RCBA32(0x0218) = 0x00020504;
+	/*./inteltool -r |grep -i 0x0220
+	      0x0220: 0x000000c5 */
+	RCBA8(0x0220) = 0xc5; /*c5;*/
+	reg32 = RCBA32(0x3410);
+	reg32 |= (1 << 6);
+	RCBA32(0x3410) = reg32;
+	reg32 = RCBA32(0x3430);
+	reg32 &= ~(3 << 0);
+	reg32 |= (1 << 0);
+	RCBA32(0x3430) = reg32;
+	RCBA32(FD) |= (1 << 0);
+	/*./inteltool -r |grep -i 0x0200
+		0x0130: 0x02000002
+		0x0200: 0x01102008 */
+//	RCBA16(0x0200) = 0x0110;
+	RCBA32(0x0200) = 0x01102008;
+	/*./inteltool -r |grep -i 0x2028
+	0x2028: 0x0038f221
+	./inteltool -r |grep -i 0x2024
+	0x2024: 0x0d303000*/
+	RCBA8(0x2027) = 0x00;
+	RCBA16(0x3e08) |= (1 << 7);
+	RCBA16(0x3e48) |= (1 << 7);
+	RCBA32(0x3e0e) |= (1 << 7);
+	RCBA32(0x3e4e) |= (1 << 7);
+	// next step only on ich7m b0 and later:
+	reg32 = RCBA32(0x2034);
+	reg32 &= ~(0x0f << 16);
+	reg32 |= (5 << 16);
+	RCBA32(0x2034) = reg32;
+}
+void main(unsigned long bist)
+{
+	u32 reg32;
+	int boot_mode = 0;
+	int cbmem_was_initted;
+	if (bist == 0)
+	enable_lapic();
+	ich7_enable_lpc();
+	/* Set up the console */
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+	if (MCHBAR16(SSKPD) == 0xCAFE) {
+		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
+		outb(0x6, 0xcf9);
+		while (1) asm("hlt");
+	}
+	/* Perform some early chipset initialization required
+	 * before RAM initialization can work
+	 */
+	i945_early_initialization();
+	/* Read PM1_CNT */
+	reg32 = inl(DEFAULT_PMBASE + 0x04);
+	printk(BIOS_DEBUG, "PM1_CNT....: %08x\n", reg32);
+	if (((reg32 >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+		boot_mode = 2;
+		/* Clear SLP_TYPE. This will break stage2 but
+		 * we care for that when we get there.
+		 */
+		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+#else
+		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif /* CONFIG_HAVE_ACPI_RESUME */
+	}
+	/* Enable SPD ROMs and DDR-II DRAM */
+	enable_smbus();
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+	dump_spd_registers();
+#endif
+	sdram_initialize(boot_mode, NULL);
+	/* Perform some initialization that must run before stage2 */
+	early_ich7_init();
+	/* This should probably go away. Until now it is required
+	 * and mainboard specific
+	 */
+	rcba_config();
+	/* Chipset Errata! */
+	fixup_i945_errata();
+	/* Initialize the internal PCIe links before we go into stage2 */
+	i945_late_initialization();
+#if !CONFIG_HAVE_ACPI_RESUME
+	sdram_dump_mchbar_registers();
+#endif 	/* !CONFIG_HAVE_ACPI_RESUME */
+	quick_ram_check();
+	MCHBAR16(SSKPD) = 0xCAFE;
+	cbmem_was_initted = !cbmem_recovery(boot_mode==2);
+#if CONFIG_HAVE_ACPI_RESUME /* !CONFIG_HAVE_ACPI_RESUME */
+	/* If there is no high memory area, we didn't boot before, so
+	 * this is not a resume. In that case we just create the cbmem toc.
+	 */
+	if ((boot_mode == 2) && cbmem_was_initted) {
+		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+		/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+		 * through stage 2. We could keep stuff like stack and heap in high tables
+		 * memory completely, but that's a wonderful clean up task for another
+		 * day.
+		 */
+		if (resume_backup_memory)
+			memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+		/* Magic for S3 resume */
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
+	}
+#endif /* CONFIG_HAVE_ACPI_RESUME */
+}
diff --git a/src/mainboard/nec/945g-m4/smihandler.c b/src/mainboard/nec/945g-m4/smihandler.c
new file mode 100644
index 0000000..d1f4f7b
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/smihandler.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/i82801gx/nvs.h>
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+	switch (smif) {
+	case 0x99:
+		printk(BIOS_DEBUG, "Sample\n");
+		gnvs->smif = 0;
+		break;
+	default:
+		return 0;
+	}
+
+	/* On success, the IO Trap Handler returns 0
+	 * On failure, the IO Trap Handler returns a value != 0
+	 *
+	 * For now, we force the return value to 0 and log all traps to
+	 * see what's going on.
+	 */
+	//gnvs->smif = 0;
+	return 1;
+}
diff --git a/src/mainboard/nec/945g-m4/superio_hwm.c b/src/mainboard/nec/945g-m4/superio_hwm.c
new file mode 100644
index 0000000..622f8e8
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/superio_hwm.c
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <device/device.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <pc80/mc146818rtc.h>
+
+#include "superio_hwm.h"
+
+/* Hardware Monitor */
+
+#define FAN_CRUISE_CONTROL_DISABLED	0
+#define FAN_CRUISE_CONTROL_SPEED	1
+#define FAN_CRUISE_CONTROL_THERMAL	2
+
+#define FAN_SPEED_5625	0
+//#define FAN_TEMPERATURE_30DEGC	0
+
+#define HWM_BASE 0x290
+
+static void hwm_write(u8 reg, u8 value)
+{
+	outb(reg, HWM_BASE + 0x05); // Index port
+	outb(value, HWM_BASE + 0x06); // Data port
+}
+
+static void hwm_bank(u8 bank)
+{
+	hwm_write(0x2e, bank);
+}
+
+struct fan_speed {
+	u8 fan_in;
+	u16 fan_speed;
+};
+
+// FANIN Target Speed Register
+// FANIN = 337500 / RPM
+struct fan_speed fan_speeds[] = {
+	{ 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 },
+	{ 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 },
+	{ 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 },
+	{ 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 }
+};
+
+struct temperature {
+	u8 deg_celsius;
+	u8 deg_fahrenheit;
+};
+
+struct temperature temperatures[] = {
+	{ 30,  86 }, { 33,  91 }, { 36,  96 }, { 39, 102 },
+	{ 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 },
+	{ 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 },
+	{ 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 }
+};
+
+void hwm_setup(void)
+{
+	int cpufan_control = 0, sysfan_control = 0;
+	int cpufan_speed = 0, sysfan_speed = 0;
+	int cpufan_temperature = 0, sysfan_temperature = 0;
+
+	if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS)
+		cpufan_control = FAN_CRUISE_CONTROL_DISABLED;
+	if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS)
+		cpufan_speed = FAN_SPEED_5625;
+	//if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS)
+	//	cpufan_temperature = FAN_TEMPERATURE_30DEGC;
+
+	if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS)
+		sysfan_control = FAN_CRUISE_CONTROL_DISABLED;
+	if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS)
+		sysfan_speed = FAN_SPEED_5625;
+	//if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS)
+	//	sysfan_temperature = FAN_TEMPERATURE_30DEGC;
+
+	// hwm_write(0x31, 0x20); // AVCC high limit
+	// hwm_write(0x34, 0x06); // VIN2 low limit
+
+	hwm_bank(0);
+	hwm_write(0x59, 0x20); // Diode Selection
+	hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor
+
+	hwm_bank(4);
+	hwm_write(0x54, 0xf1); // SYSTIN temperature offset
+	hwm_write(0x55, 0x19); // CPUTIN temperature offset
+	hwm_write(0x56, 0xfc); // AUXTIN temperature offset
+
+	hwm_bank(0x80); // Default
+
+	u8 fan_config = 0;
+	// 00 FANOUT is Manual Mode
+	// 01 FANOUT is Thermal Cruise Mode
+	// 10 FANOUT is Fan Speed Cruise Mode
+	switch (cpufan_control) {
+	case FAN_CRUISE_CONTROL_SPEED:	 fan_config |= (2 << 4); break;
+	case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break;
+	}
+	switch (sysfan_control) {
+	case FAN_CRUISE_CONTROL_SPEED:	 fan_config |= (2 << 2); break;
+	case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break;
+	}
+	// This register must be written first
+	hwm_write(0x04, fan_config);
+
+	switch (cpufan_control) {
+	case FAN_CRUISE_CONTROL_SPEED:
+		printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n",
+				fan_speeds[cpufan_speed].fan_speed);
+		hwm_write(0x06, fan_speeds[cpufan_speed].fan_in);  // CPUFANIN target speed
+		break;
+	case FAN_CRUISE_CONTROL_THERMAL:
+		printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n",
+				temperatures[cpufan_temperature].deg_celsius,
+				temperatures[cpufan_temperature].deg_fahrenheit);
+		hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius);  // CPUFANIN target temperature
+		break;
+	}
+
+	switch (sysfan_control) {
+	case FAN_CRUISE_CONTROL_SPEED:
+		printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n",
+				fan_speeds[sysfan_speed].fan_speed);
+		hwm_write(0x05, fan_speeds[sysfan_speed].fan_in);  // SYSFANIN target speed
+		break;
+	case FAN_CRUISE_CONTROL_THERMAL:
+		printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n",
+				temperatures[sysfan_temperature].deg_celsius,
+				temperatures[sysfan_temperature].deg_fahrenheit);
+		hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature
+		break;
+	}
+
+	hwm_write(0x0e, 0x02); // Fan Output Step Down Time
+	hwm_write(0x0f, 0x02); // Fan Output Step Up Time
+
+	hwm_write(0x47, 0xaf); // FAN divisor register
+	hwm_write(0x4b, 0x84); // AUXFANIN speed divisor
+
+	hwm_write(0x40, 0x01); // Init, but no SMI#
+}
diff --git a/src/mainboard/nec/945g-m4/superio_hwm.h b/src/mainboard/nec/945g-m4/superio_hwm.h
new file mode 100644
index 0000000..346b97c
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/superio_hwm.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_HWM_H
+#define SUPERIO_HWM_H
+
+void hwm_setup(void);
+
+#endif /* SUPERIO_HWM_H */
diff --git a/src/mainboard/nec/Kconfig b/src/mainboard/nec/Kconfig
index 525121f..b8bb2d6 100644
--- a/src/mainboard/nec/Kconfig
+++ b/src/mainboard/nec/Kconfig
@@ -24,9 +24,13 @@ choice
 config BOARD_NEC_POWERMATE_2000
 	bool "PowerMate 2000"
 
+config BOARD_NEC_945G_M4
+	bool "945g-m4"
+
 endchoice
 
 source "src/mainboard/nec/powermate2000/Kconfig"
+source "src/mainboard/nec/945g-m4/Kconfig"
 
 config MAINBOARD_VENDOR
 	string



More information about the coreboot-gerrit mailing list