[coreboot-gerrit] Patch set updated for coreboot: f705375 mainboard/jetway/nf81-t56n-lf: Major ACPI board rework

Edward O'Callaghan (eocallaghan@alterapraxis.com) gerrit at coreboot.org
Sat May 31 04:40:23 CEST 2014


Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5887

-gerrit

commit f70537583b1e2dcaa81b5a1e6cfa33a65ba670ff
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Sat May 31 10:09:52 2014 +1000

    mainboard/jetway/nf81-t56n-lf: Major ACPI board rework
    
    NOTFORMERGE yet
    
    Change-Id: I500ebbafd5e9400f9a9dbfe8240fdcdccb6bb900
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl     | 110 ++++++++++++-----
 .../jetway/nf81-t56n-lf/acpi/mainboard.asl         |   6 +
 src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl |  76 +++++++++++-
 src/mainboard/jetway/nf81-t56n-lf/dsdt.asl         | 133 +++++++++++++++++++++
 4 files changed, 288 insertions(+), 37 deletions(-)

diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl
index 6ad1ad4..42a0494 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl
+++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,67 +18,110 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-Scope(\_GPE) {	/* Start Scope GPE */
+Scope(\_GPE)
+{
+	OperationRegion (IP, SystemIO, 0x0225, 0x02)
+	Field (IP, ByteAcc, NoLock, Preserve)
+	{
+		INDX,   8,
+		DAT0,   8
+	}
 
 	/*  General event 3  */
-	Method(_L03) {
-		/* DBGO("\\_GPE\\_L00\n") */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	Method(_L03)
+	{
+		Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 	}
 
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
+	Method (_L04, 0, NotSerialized) /* _Lxx: Level-Triggered GPE */
+	{
+		Notify (\_SB.PCI0.P0PC, 0x02)
+		Notify (\_SB.PWRB, 0x02)
 	}
 
 	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
+	Method(_L09, 0, NotSerialized)
+	{
 		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
+		Store (GBYT (0x66), Local0)
+		If (LNotEqual (And (Local0, 0x02), Zero))
+		{
+			Notify (\_TZ.THRM, 0x80)
+		}
+	}
+
+	Method (GBYT, 1, NotSerialized)
+	{
+		Store (Arg0, INDX)
+		Store (DAT0, Local0)
+		Return (Local0)
 	}
 
 	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	Method(_L0B, 0, NotSerialized) {
+		Notify (\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify (\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify (\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify (\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify (\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify (\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify (\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	Method(_L0F) {
+		Notify (\_SB.PCI0.PE20, 0x02)
+		Notify (\_SB.PWRB, 0x02)
 	}
 
 	/*  ExtEvent0 SCI event  */
 	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
+		Notify (\_SB.PCI0.PE21, 0x02)
+		Notify (\_SB.PWRB, 0x02)
 	}
 
-
 	/*  ExtEvent1 SCI event  */
 	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
+		Notify (\_SB.PCI0.PE22, 0x02)
+		Notify (\_SB.PWRB, 0x02)
+	}
+
+	Method(_L12) {
+		Notify (\_SB.PCI0.PE23, 0x02)
+		Notify (\_SB.PWRB, 0x02)
 	}
 
 	/*  GPIO0 or GEvent8 event  */
 	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify (\_SB.PCI0.BR15, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify (\_SB.PCI0.PCE6, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 	}
 
 	/*  Azalia SCI event  */
 	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify (\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	Method (_L1D, 0, NotSerialized)
+	{
+		/* call SIO method on PS/2 Mouse/keyboard event */
+		/* \_SB.PCI0.SBRG.SIOH () */
+		Notify (\_SB.PWRB, 0x02)
 	}
-} 	/* End Scope GPE */
+
+	Device (PWRB)
+	{
+		Name (_HID, EisaId ("PNP0C0C")) // _HID: Hardware ID
+		Name (_UID, 0xAA) // _UID: Unique ID
+		Name (_STA, 0x0B) // _STA: Status
+		Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+		{
+			Return (GPRW (0x1D, 0x03))
+		}
+	}
+}	/* End Scope GPE */
 
 /* Contains the GPEs for USB overcurrent */
 #include "usb_oc.asl"
-
diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl
index 47c17df..af37965 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl
+++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl
@@ -35,6 +35,12 @@ Name(OSTP, 3)
 Name(OSV, Ones)	/* Assume nothing */
 Name(PMOD, One)	/* Assume APIC */
 
+Name (TPCH, Zero)
+Name (SS1, Zero)
+Name (SS2, Zero)
+Name (SS3, One)
+Name (SS4, One)
+
 Scope(\_SB) {
 	Method(CkOT, 0, NotSerialized)
 	{
diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl
index 2f50475..b73a7ce 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl
+++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl
@@ -1,6 +1,8 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -15,7 +17,73 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-/* Thermal Zones have been #if 0 for a long time.
- * Removing it for now because it doesn't seem to
- * do anything when enabled anyway.
- */
+/* Thermal Zones. */
+
+Scope (\_TZ)
+{
+    OperationRegion (IP, SystemIO, 0x0225, 0x02)
+    Field (IP, ByteAcc, NoLock, Preserve)
+    {
+        INDX, 8,
+        DAT0, 8
+    }
+
+    ThermalZone (THRM)
+    {
+        Method (KELV, 1, NotSerialized)
+        {
+            Store (Arg0, Local1)
+            Multiply (0x0A, Local1, Local1)
+            Add (Local1, 0x0AAC, Local1)
+            Return (Local1)
+        }
+
+        Method (_TMP, 0, NotSerialized) // _TMP: Temperature
+        {
+            If (LEqual (TPCH, One))
+            {
+                While (LGreater (GBYT (0x7A), 0x7E))
+                {
+                    Store (GBYT (0x7A), DBG8)
+                    Sleep (0xFA)
+                    Store (One, Local1)
+                    Multiply (0x0A, Local1, Local1)
+                    Add (Local1, 0x0AAC, Local1)
+                    Return (Local1)
+                }
+            }
+
+            Return (KELV (CTMP ()))
+        }
+
+        Method (_CRT, 0, NotSerialized) // _CRT: Critical Temperature
+        {
+            Return (KELV (STMP ()))
+        }
+
+        Method (STMP, 0, NotSerialized)
+        {
+            Store (GBYT (0x82), Local0)
+            Return (Local0)
+        }
+
+        Method (CTMP, 0, NotSerialized)
+        {
+            Store (GBYT (0x7A), Local0)
+            Store (Local0, DBG8)
+            If (LGreaterEqual (Local0, 0x65))
+            {
+                Store (0x30, Local0)
+            }
+
+            Return (Local0)
+        }
+
+        Method (GBYT, 1, NotSerialized)
+        {
+            Store (Arg0, INDX)
+            Store (DAT0, Local0)
+            Return (Local0)
+        }
+    }
+}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl
index a650bca..45d5650 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl
+++ b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -47,6 +48,138 @@ DefinitionBlock (
 			/* Describe the AMD Fusion Controller Hub Southbridge */
 			#include <southbridge/amd/cimx/sb800/acpi/fch.asl>
 
+			Device (BR15)
+			{
+				Name (_ADR, 0x00050000) // _ADR: Address
+				Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+				{
+					Return (GPRW (0x18, 0x04))
+				}
+
+				Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+				{
+					If (PR0)
+					{
+						Return (APR0)
+					}
+
+					Return (PR0)
+				}
+			}
+
+			Device (PCE6)
+			{
+				Name (_ADR, 0x00060000) // _ADR: Address
+				Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+				{
+					Return (GPRW (0x18, 0x04))
+				}
+
+				Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+				{
+					If (PR0)
+					{
+						Return (APR0)
+					}
+
+					Return (PR0)
+				}
+			}
+
+			Device (PCE7)
+			{
+				Name (_ADR, 0x00070000) // _ADR: Address
+				Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+				{
+					If (PR0)
+					{
+						Return (APR0)
+					}
+
+					Return (PR0)
+				}
+			}
+
+			Device (PCE8)
+			{
+				Name (_ADR, 0x00080000) // _ADR: Address
+				Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+				{
+					If (PR0)
+					{
+						Return (APR0)
+					}
+
+					Return (PR0)
+				}
+			}
+
+			Device (P0PC)
+			{
+				Name (_ADR, 0x00140004) // _ADR: Address
+				Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+				{
+					Return (GPRW (0x04, 0x04))
+				}
+
+				Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+				{
+					If (PR0)
+					{
+						Return (APR0)
+					}
+
+					Return (PR0)
+				}
+			}
+
+			Device (GEC)
+			{
+				Name (_ADR, 0x00140006) // _ADR: Address
+				Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+				{
+					Return (GPRW (0x13, 0x04))
+				}
+			}
+
+			Name (PRWP, Package (0x02)
+			{
+				Zero,
+				Zero
+			})
+
+			Method (GPRW, 2, NotSerialized)
+			{
+				Store (Arg0, Index (PRWP, Zero))
+				Store (ShiftLeft (SS1, One), Local0)
+				Or (Local0, ShiftLeft (SS2, 0x02), Local0)
+				Or (Local0, ShiftLeft (SS3, 0x03), Local0)
+				Or (Local0, ShiftLeft (SS4, 0x04), Local0)
+				If (And (ShiftLeft (One, Arg1), Local0))
+				{
+					Store (Arg1, Index (PRWP, One))
+				}
+				Else
+				{
+					ShiftRight (Local0, One, Local0)
+					If (LOr (LEqual (CkOT (), One), LEqual (CkOT (), 0x02)))
+					{
+						FindSetLeftBit (Local0, Index (PRWP, One))
+					}
+					Else
+					{
+						FindSetRightBit (Local0, Index (PRWP, One))
+					}
+				}
+
+				Return (PRWP)
+			}
+
+			OperationRegion (DEB0, SystemIO, 0x80, One)
+			Field (DEB0, ByteAcc, NoLock, Preserve)
+			{
+					DBG8, 8
+			}
 		}
 	}   /* End Scope(_SB)  */
 



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