[coreboot-gerrit] New patch to review for coreboot: ab7dbde inteltool/sandybridge: Kill mch_registers codepath.
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Tue Nov 4 21:23:48 CET 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7324
-gerrit
commit ab7dbdeedac495f96f2979578f5e7d2d4adf5e9b
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Tue Nov 4 21:05:12 2014 +0100
inteltool/sandybridge: Kill mch_registers codepath.
It never worked.
Change-Id: Ic68614bb8ed481babf54b4f9d8db00635755f4d1
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
util/inteltool/memory.c | 83 ++-----------------------------------------------
1 file changed, 3 insertions(+), 80 deletions(-)
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index c755de7..14213e3 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -23,47 +23,6 @@
#include <inttypes.h>
#include "inteltool.h"
-static const io_register_t sandybridge_mch_registers[] = {
-/* Channel 0 */
- { 0x4000, 4, "TC_DBP_C0" }, // Timing of DDR Bin Parameters
- { 0x4004, 4, "TC_RAP_C0" }, // Timing of DDR Regular Access Parameters
- { 0x4028, 4, "SC_IO_LATENCY_C0" }, // IO Latency Configuration
- { 0x42A4, 4, "TC_SRFTP_C0" }, // Self-Refresh Timing Parameters
- { 0x40B0, 4, "PM_PDWN_config_C0" }, // Power-down Configuration
- { 0x4294, 4, "TC_RFP_C0" }, // Refresh Parameters
- { 0x4298, 4, "TC_RFTP_C0" }, // Refresh Timing Parameters
-/* Channel 1 */
- { 0x4400, 4, "TC_DBP_C1" }, // Timing of DDR Bin Parameters
- { 0x4404, 4, "TC_RAP_C1" }, // Timing of DDR Regular Access Parameters
- { 0x4428, 4, "SC_IO_LATENCY_C1" }, // IO Latency Configuration
- { 0x46A4, 4, "TC_SRFTP_C1" }, // Self-Refresh Timing Parameters
- { 0x44B0, 4, "PM_PDWN_config_C1" }, // Power-down Configuration
- { 0x4694, 4, "TC_RFP_C1" }, // Refresh Parameters
- { 0x4698, 4, "TC_RFTP_C1" }, // Refresh Timing Parameters
-/* Integrated Memory Peripheral Hub (IMPH) */
- { 0x740C, 4, "CRDTCTL3" }, // Credit Control 3
-/* Common Registers */
- { 0x5000, 4, "MAD_CHNL" }, // Address decoder Channel Configuration
- { 0x5004, 4, "MAD_DIMM_ch0" }, // Address Decode Channel 0
- { 0x5008, 4, "MAD_DIMM_ch1" }, // Address Decode Channel 1
- { 0x5060, 4, "PM_SREF_config" }, // Self Refresh Configuration
-/* MMIO Registers Broadcast Group */
- { 0x4CB0, 4, "PM_PDWN_config" }, // Power-down Configuration
- { 0x4F84, 4, "PM_CMD_PWR" }, // Power Management Command Power
- { 0x4F88, 4, "PM_BW_LIMIT_config" }, // BW Limit Configuration
- { 0x4F8C, 4, "RESERVED" }, // Reserved, default value - 0xFF1D1519
-/* PCU MCHBAR Registers */
- { 0x5880, 4, "MEM_TRML_ESTIMATION_CONFIG" }, // Memory Thermal Estimation Configuration
- { 0x5884, 4, "RESERVED" }, // Reserved
- { 0x5888, 4, "MEM_TRML_THRESHOLDS_CONFIG" }, // Memory Thermal Thresholds Configuration
- { 0x58A0, 4, "MEM_TRML_STATUS_REPORT" }, // Memory Thermal Status Report
- { 0x58A4, 4, "MEM_TRML_TEMPERATURE_REPORT" }, // Memory Thermal Temperature Report
- { 0x58A8, 4, "MEM_TRML_INTERRUPT" }, // Memory Thermal Interrupt
- { 0x5948, 4, "GT_PERF_STATUS" }, // GT Performance Status
- { 0x5998, 4, "RP_STATE_CAP" }, // RP State Capability
- { 0x5D10, 8, "SSKPD" }, // Sticky Scratchpad Data
-};
-
volatile uint8_t *mchbar;
static void write_mchbar32 (uint32_t addr, uint32_t val)
@@ -156,7 +115,6 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
{
int i, size = (16 * 1024);
uint64_t mchbar_phys;
- const io_register_t *mch_registers = NULL;
struct pci_dev *nb_device6; /* "overflow device" on i865 */
uint16_t pcicmd6;
@@ -246,11 +204,8 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
mchbar_phys = pci_read_long(nb, 0x48);
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */
- mch_registers = NULL; /* TODO: 322812 */
break;
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
- mch_registers = sandybridge_mch_registers;
- size = ARRAY_SIZE(sandybridge_mch_registers);
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A: /* pretty printing not implemented yet */
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B:
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C:
@@ -279,41 +234,9 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
else
printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys);
- if (mch_registers != NULL) {
- printf("%d registers:\n", size);
- for (i = 0; i < size; i++) {
- switch (mch_registers[i].size) {
- case 8:
- printf("mchbase+0x%04x: 0x%016"PRIx64" (%s)\n",
- mch_registers[i].addr,
- *(uint64_t *)(mchbar+mch_registers[i].addr),
- mch_registers[i].name);
- break;
- case 4:
- printf("mchbase+0x%04x: 0x%08"PRIx32" (%s)\n",
- mch_registers[i].addr,
- *(uint32_t *)(mchbar+mch_registers[i].addr),
- mch_registers[i].name);
- break;
- case 2:
- printf("mchbase+0x%04x: 0x%04"PRIx16" (%s)\n",
- mch_registers[i].addr,
- *(uint16_t *)(mchbar+mch_registers[i].addr),
- mch_registers[i].name);
- break;
- case 1:
- printf("mchbase+0x%04x: 0x%02"PRIx8" (%s)\n",
- mch_registers[i].addr,
- *(uint8_t *)(mchbar+mch_registers[i].addr),
- mch_registers[i].name);
- break;
- }
- }
- } else {
- for (i = 0; i < size; i += 4) {
- if (*(uint32_t *)(mchbar + i))
- printf("0x%04x: 0x%08"PRIx32"\n", i, *(uint32_t *)(mchbar+i));
- }
+ for (i = 0; i < size; i += 4) {
+ if (*(uint32_t *)(mchbar + i))
+ printf("0x%04x: 0x%08"PRIx32"\n", i, *(uint32_t *)(mchbar+i));
}
if (nb->device_id == PCI_DEVICE_ID_INTEL_CORE_1ST_GEN) {
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