[coreboot-gerrit] Patch set updated for coreboot: eff094f haswell: Move to implicit length patching
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Tue Nov 4 23:48:34 CET 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7327
-gerrit
commit eff094f36fd4b760246bf89c3019c65e4abb86f3
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Tue Nov 4 21:10:59 2014 +0100
haswell: Move to implicit length patching
Change-Id: I662ba2a08f9a176a84b8318c8004aa5db7239567
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/cpu/intel/haswell/acpi.c | 112 +++++++++++++++-------------------
src/southbridge/intel/lynxpoint/lpc.c | 8 +--
2 files changed, 52 insertions(+), 68 deletions(-)
diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c
index 544436f..6323d27 100644
--- a/src/cpu/intel/haswell/acpi.c
+++ b/src/cpu/intel/haswell/acpi.c
@@ -50,10 +50,10 @@ static int get_cores_per_package(void)
return cores;
}
-static int generate_cstate_entries(acpi_cstate_t *cstates,
+static void generate_cstate_entries(acpi_cstate_t *cstates,
int c1, int c2, int c3)
{
- int length, cstate_count = 0;
+ int cstate_count = 0;
/* Count number of active C-states */
if (c1 > 0)
@@ -63,74 +63,70 @@ static int generate_cstate_entries(acpi_cstate_t *cstates,
if (c3 > 0)
++cstate_count;
if (!cstate_count)
- return 0;
+ return;
- length = acpigen_write_package(cstate_count + 1);
- length += acpigen_write_byte(cstate_count);
+ acpigen_write_package(cstate_count + 1);
+ acpigen_write_byte(cstate_count);
/* Add an entry if the level is enabled */
if (c1 > 0) {
cstates[c1].ctype = 1;
- length += acpigen_write_CST_package_entry(&cstates[c1]);
+ acpigen_write_CST_package_entry(&cstates[c1]);
}
if (c2 > 0) {
cstates[c2].ctype = 2;
- length += acpigen_write_CST_package_entry(&cstates[c2]);
+ acpigen_write_CST_package_entry(&cstates[c2]);
}
if (c3 > 0) {
cstates[c3].ctype = 3;
- length += acpigen_write_CST_package_entry(&cstates[c3]);
+ acpigen_write_CST_package_entry(&cstates[c3]);
}
- acpigen_patch_len(length - 1);
- return length;
+ acpigen_pop_len();
}
-static int generate_C_state_entries(void)
+static void generate_C_state_entries(void)
{
struct cpu_info *info;
struct cpu_driver *cpu;
- int len, lenif;
struct device *lapic;
struct cpu_intel_haswell_config *conf = NULL;
/* Find the SpeedStep CPU in the device tree using magic APIC ID */
lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
if (!lapic)
- return 0;
+ return;
conf = lapic->chip_info;
if (!conf)
- return 0;
+ return;
/* Find CPU map of supported C-states */
info = cpu_info();
if (!info)
- return 0;
+ return;
cpu = find_cpu_driver(info->cpu);
if (!cpu || !cpu->cstates)
- return 0;
+ return;
- len = acpigen_emit_byte(0x14); /* MethodOp */
- len += acpigen_write_len_f(); /* PkgLength */
- len += acpigen_emit_namestring("_CST");
- len += acpigen_emit_byte(0x00); /* No Arguments */
+ acpigen_emit_byte(0x14); /* MethodOp */
+ acpigen_write_len_f(); /* PkgLength */
+ acpigen_emit_namestring("_CST");
+ acpigen_emit_byte(0x00); /* No Arguments */
/* If running on AC power */
- len += acpigen_emit_byte(0xa0); /* IfOp */
- lenif = acpigen_write_len_f(); /* PkgLength */
- lenif += acpigen_emit_namestring("PWRS");
- lenif += acpigen_emit_byte(0xa4); /* ReturnOp */
- lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower,
+ acpigen_emit_byte(0xa0); /* IfOp */
+ acpigen_write_len_f(); /* PkgLength */
+ acpigen_emit_namestring("PWRS");
+ acpigen_emit_byte(0xa4); /* ReturnOp */
+ generate_cstate_entries(cpu->cstates, conf->c1_acpower,
conf->c2_acpower, conf->c3_acpower);
- acpigen_patch_len(lenif - 1);
- len += lenif;
+ acpigen_pop_len();
/* Else on battery power */
- len += acpigen_emit_byte(0xa4); /* ReturnOp */
- len += generate_cstate_entries(cpu->cstates, conf->c1_battery,
+ acpigen_emit_byte(0xa4); /* ReturnOp */
+ generate_cstate_entries(cpu->cstates, conf->c1_battery,
conf->c2_battery, conf->c3_battery);
- acpigen_patch_len(len - 1);
- return len;
+ acpigen_pop_len();
}
static acpi_tstate_t tss_table_fine[] = {
@@ -162,31 +158,27 @@ static acpi_tstate_t tss_table_coarse[] = {
{ 13, 125, 0, 0x19, 0 },
};
-static int generate_T_state_entries(int core, int cores_per_package)
+static void generate_T_state_entries(int core, int cores_per_package)
{
- int len;
-
/* Indicate SW_ALL coordination for T-states */
- len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
+ acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
/* Indicate FFixedHW so OS will use MSR */
- len += acpigen_write_empty_PTC();
+ acpigen_write_empty_PTC();
/* Set a T-state limit that can be modified in NVS */
- len += acpigen_write_TPC("\\TLVL");
+ acpigen_write_TPC("\\TLVL");
/*
* CPUID.(EAX=6):EAX[5] indicates support
* for extended throttle levels.
*/
if (cpuid_eax(6) & (1 << 5))
- len += acpigen_write_TSS_package(
+ acpigen_write_TSS_package(
ARRAY_SIZE(tss_table_fine), tss_table_fine);
else
- len += acpigen_write_TSS_package(
+ acpigen_write_TSS_package(
ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
-
- return len;
}
static int calculate_power(int tdp, int p1_ratio, int ratio)
@@ -210,9 +202,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio)
return (int)power;
}
-static int generate_P_state_entries(int core, int cores_per_package)
+static void generate_P_state_entries(int core, int cores_per_package)
{
- int len, len_pss;
int ratio_min, ratio_max, ratio_turbo, ratio_step;
int coord_type, power_max, power_unit, num_entries;
int ratio, power, clock, clock_max;
@@ -247,16 +238,16 @@ static int generate_P_state_entries(int core, int cores_per_package)
power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
/* Write _PCT indicating use of FFixedHW */
- len = acpigen_write_empty_PCT();
+ acpigen_write_empty_PCT();
/* Write _PPC with no limit on supported P-state */
- len += acpigen_write_PPC_NVS();
+ acpigen_write_PPC_NVS();
/* Write PSD indicating configured coordination type */
- len += acpigen_write_PSD_package(core, 1, coord_type);
+ acpigen_write_PSD_package(core, 1, coord_type);
/* Add P-state entries in _PSS table */
- len += acpigen_write_name("_PSS");
+ acpigen_write_name("_PSS");
/* Determine ratio points */
ratio_step = PSS_RATIO_STEP;
@@ -269,13 +260,13 @@ static int generate_P_state_entries(int core, int cores_per_package)
/* P[T] is Turbo state if enabled */
if (get_turbo_state() == TURBO_ENABLED) {
/* _PSS package count including Turbo */
- len_pss = acpigen_write_package(num_entries + 2);
+ acpigen_write_package(num_entries + 2);
msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
ratio_turbo = msr.lo & 0xff;
/* Add entry for Turbo ratio */
- len_pss += acpigen_write_PSS_package(
+ acpigen_write_PSS_package(
clock_max + 1, /*MHz*/
power_max, /*mW*/
PSS_LATENCY_TRANSITION, /*lat1*/
@@ -284,11 +275,11 @@ static int generate_P_state_entries(int core, int cores_per_package)
ratio_turbo << 8); /*status*/
} else {
/* _PSS package count without Turbo */
- len_pss = acpigen_write_package(num_entries + 1);
+ acpigen_write_package(num_entries + 1);
}
/* First regular entry is max non-turbo ratio */
- len_pss += acpigen_write_PSS_package(
+ acpigen_write_PSS_package(
clock_max, /*MHz*/
power_max, /*mW*/
PSS_LATENCY_TRANSITION, /*lat1*/
@@ -304,7 +295,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
power = calculate_power(power_max, ratio_max, ratio);
clock = ratio * HASWELL_BCLK;
- len_pss += acpigen_write_PSS_package(
+ acpigen_write_PSS_package(
clock, /*MHz*/
power, /*mW*/
PSS_LATENCY_TRANSITION, /*lat1*/
@@ -314,15 +305,11 @@ static int generate_P_state_entries(int core, int cores_per_package)
}
/* Fix package length */
- len_pss--;
- acpigen_patch_len(len_pss);
-
- return len + len_pss;
+ acpigen_pop_len();
}
void generate_cpu_entries(void)
{
- int len_pr;
int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6;
int totalcores = dev_count_cpu();
int cores_per_package = get_cores_per_package();
@@ -339,23 +326,22 @@ void generate_cpu_entries(void)
}
/* Generate processor \_PR.CPUx */
- len_pr = acpigen_write_processor(
+ acpigen_write_processor(
(cpuID-1)*cores_per_package+coreID-1,
pcontrol_blk, plen);
/* Generate P-state tables */
- len_pr += generate_P_state_entries(
+ generate_P_state_entries(
coreID-1, cores_per_package);
/* Generate C-state tables */
- len_pr += generate_C_state_entries();
+ generate_C_state_entries();
/* Generate T-state tables */
- len_pr += generate_T_state_entries(
+ generate_T_state_entries(
cpuID-1, cores_per_package);
- len_pr--;
- acpigen_patch_len(len_pr);
+ acpigen_pop_len();
}
}
}
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index a202424..563cb0a 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -755,8 +755,6 @@ static void southbridge_inject_dsdt(void)
}
if (gnvs) {
- int scopelen;
-
acpi_create_gnvs(gnvs);
gnvs->apic = 1;
@@ -775,9 +773,9 @@ static void southbridge_inject_dsdt(void)
smm_setup_structures(gnvs, NULL, NULL);
/* Add it to DSDT. */
- scopelen = acpigen_write_scope("\\");
- scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs);
- acpigen_patch_len(scopelen - 1);
+ acpigen_write_scope("\\");
+ acpigen_write_name_dword("NVSA", (u32) gnvs);
+ acpigen_pop_len();
}
}
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